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51ecb29f7a
Address bytes shifted with a single 64 bit page table entry (any page table level) has been always hard coded as 3 (aka 2^3 = 8). Although intuitive it is not very readable or easy to reason about. Besides it is going to change with D128, where each 128 bit page table entry will shift address bytes by 4 (aka 2^4 = 16) instead. Let's just formalise this address bytes shift value into a new macro called PTDESC_ORDER establishing a logical abstraction, thus improving readability as well. While here re-organize EARLY_LEVEL macro along with its dependents for better clarity. This does not cause any functional change. Also replace all (PAGE_SHIFT - PTDESC_ORDER) instances with PTDESC_TABLE_SHIFT. Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com> Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Konovalov <andreyknvl@gmail.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: kasan-dev@googlegroups.com Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20250311045710.550625-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
106 lines
3.1 KiB
C
106 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright 2023 Google LLC
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// Author: Ard Biesheuvel <ardb@google.com>
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#include <linux/types.h>
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#include <linux/sizes.h>
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#include <asm/memory.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include "pi.h"
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/**
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* map_range - Map a contiguous range of physical pages into virtual memory
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*
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* @pte: Address of physical pointer to array of pages to
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* allocate page tables from
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* @start: Virtual address of the start of the range
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* @end: Virtual address of the end of the range (exclusive)
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* @pa: Physical address of the start of the range
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* @prot: Access permissions of the range
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* @level: Translation level for the mapping
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* @tbl: The level @level page table to create the mappings in
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* @may_use_cont: Whether the use of the contiguous attribute is allowed
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* @va_offset: Offset between a physical page and its current mapping
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* in the VA space
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*/
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void __init map_range(u64 *pte, u64 start, u64 end, u64 pa, pgprot_t prot,
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int level, pte_t *tbl, bool may_use_cont, u64 va_offset)
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{
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u64 cmask = (level == 3) ? CONT_PTE_SIZE - 1 : U64_MAX;
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pteval_t protval = pgprot_val(prot) & ~PTE_TYPE_MASK;
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int lshift = (3 - level) * PTDESC_TABLE_SHIFT;
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u64 lmask = (PAGE_SIZE << lshift) - 1;
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start &= PAGE_MASK;
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pa &= PAGE_MASK;
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/* Advance tbl to the entry that covers start */
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tbl += (start >> (lshift + PAGE_SHIFT)) % PTRS_PER_PTE;
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/*
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* Set the right block/page bits for this level unless we are
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* clearing the mapping
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*/
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if (protval)
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protval |= (level == 2) ? PMD_TYPE_SECT : PTE_TYPE_PAGE;
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while (start < end) {
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u64 next = min((start | lmask) + 1, PAGE_ALIGN(end));
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if (level < 2 || (level == 2 && (start | next | pa) & lmask)) {
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/*
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* This chunk needs a finer grained mapping. Create a
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* table mapping if necessary and recurse.
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*/
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if (pte_none(*tbl)) {
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*tbl = __pte(__phys_to_pte_val(*pte) |
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PMD_TYPE_TABLE | PMD_TABLE_UXN);
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*pte += PTRS_PER_PTE * sizeof(pte_t);
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}
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map_range(pte, start, next, pa, prot, level + 1,
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(pte_t *)(__pte_to_phys(*tbl) + va_offset),
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may_use_cont, va_offset);
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} else {
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/*
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* Start a contiguous range if start and pa are
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* suitably aligned
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*/
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if (((start | pa) & cmask) == 0 && may_use_cont)
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protval |= PTE_CONT;
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/*
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* Clear the contiguous attribute if the remaining
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* range does not cover a contiguous block
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*/
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if ((end & ~cmask) <= start)
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protval &= ~PTE_CONT;
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/* Put down a block or page mapping */
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*tbl = __pte(__phys_to_pte_val(pa) | protval);
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}
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pa += next - start;
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start = next;
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tbl++;
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}
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}
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asmlinkage u64 __init create_init_idmap(pgd_t *pg_dir, pteval_t clrmask)
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{
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u64 ptep = (u64)pg_dir + PAGE_SIZE;
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pgprot_t text_prot = PAGE_KERNEL_ROX;
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pgprot_t data_prot = PAGE_KERNEL;
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pgprot_val(text_prot) &= ~clrmask;
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pgprot_val(data_prot) &= ~clrmask;
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map_range(&ptep, (u64)_stext, (u64)__initdata_begin, (u64)_stext,
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text_prot, IDMAP_ROOT_LEVEL, (pte_t *)pg_dir, false, 0);
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map_range(&ptep, (u64)__initdata_begin, (u64)_end, (u64)__initdata_begin,
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data_prot, IDMAP_ROOT_LEVEL, (pte_t *)pg_dir, false, 0);
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return ptep;
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}
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