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linux/Documentation/devicetree/bindings/clock
Dinh Nguyen 8cb289ed60 ARM: socfpga: dts: Add div-reg to the main_pll clocks
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-05 22:33:18 -05:00
..
2014-03-25 15:59:31 -07:00
2012-07-11 17:58:47 -07:00
2013-11-04 12:23:18 -08:00