Besar Wicaksono 49f2413f9b perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus ...

The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while
in WFI/WFE, which does not align with counting CPU_CYCLES
on a programmable counter. Add a MIDR range entry and refuse
PMCCNTR_EL0 for cycle events on affected parts so perf does
not mix the two behaviors.

Also keep PMCCNTR_EL0 unavailable to EL0 direct counter reads
on affected CPUs. When userspace counter access is enabled,
avoid setting PMUSERENR_EL0.CR for PMUs that must avoid
PMCCNTR_EL0, while still allowing direct reads from programmable
event counters. For 64-bit userspace CPU_CYCLES events on PMUs
without native long event counters, reject the event if the only
valid direct-read path would be PMCCNTR_EL0.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
Signed-off-by: Will Deacon <will@kernel.org>

2026-07-21 21:40:35 +00:00

..

arm_pmu.h

perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus

2026-07-21 21:40:35 +00:00

arm_pmuv3.h

perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control

2024-10-28 17:27:15 +00:00

riscv_pmu.h

drivers/perf: riscv: Export PMU event info function

2025-09-16 11:49:31 +05:30