Fatemeh Darbehani 7e6472966e drm/amd/display: Change min_h_sync_width from 8 to 4 ...

[Why]
Some display's hsync width is lower than the minimum dcn20 is set
to support right now. This will cause optc1_validate_timing to fail which
eventually will result in wrong set mode. This was set to 8 as per
HW team's request for no valid reason.

[How]
Changing min_h_sync_width to 4 will let us validate timing for
preffered mode and light up the headset. This change was made
to Vega 10 before for a similar issue.

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-07-18 14:18:10 -05:00

..

drm

drm/amd/display: Change min_h_sync_width from 8 to 4

2019-07-18 14:18:10 -05:00

host1x

Merge tag 'drm/tegra/for-5.3-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

2019-06-25 12:59:43 +10:00

ipu-v3

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

vga

Merge branch 'topic/remove-fbcon-notifiers' into drm-misc-next

2019-06-19 12:33:05 +02:00

Makefile

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21 10:50:46 +02:00