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651b253b80
The .shutdown operation should call dsa_switch_shutdown() just like
it is done also by the sibling lantiq_gswip driver. Not doing that
results in shutdown or reboot hanging and waiting for the CPU port
becoming free, which introduces a longer delay and a WARNING before
shutdown or reboot in case the driver is built-into the kernel.
Fix this by calling dsa_switch_shutdown() in the driver's shutdown
operation, harmonizing it with what is done in the lantiq_gswip
driver. As a side-effect this now allows to remove the previously
exported gswip_disable_switch() function which no longer got any
users.
Fixes: 22335939ec ("net: dsa: add driver for MaxLinear GSW1xx switch family")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://patch.msgid.link/77ed91a5206e5dbf5d3e83d7e364ebfda90d31fd.1765241054.git.daniel@makrotopia.org
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
300 lines
12 KiB
C
300 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef __LANTIQ_GSWIP_H
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#define __LANTIQ_GSWIP_H
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/phylink.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/swab.h>
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#include <net/dsa.h>
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/* GSWIP MDIO Registers */
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#define GSWIP_MDIO_GLOB 0x00
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#define GSWIP_MDIO_GLOB_ENABLE BIT(15)
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#define GSWIP_MDIO_CTRL 0x08
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#define GSWIP_MDIO_CTRL_BUSY BIT(12)
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#define GSWIP_MDIO_CTRL_RD BIT(11)
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#define GSWIP_MDIO_CTRL_WR BIT(10)
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#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
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#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
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#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
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#define GSWIP_MDIO_READ 0x09
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#define GSWIP_MDIO_WRITE 0x0A
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#define GSWIP_MDIO_MDC_CFG0 0x0B
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#define GSWIP_MDIO_MDC_CFG1 0x0C
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#define GSWIP_MDIO_PHYp(p) (0x15 - (p))
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#define GSWIP_MDIO_PHY_LINK_MASK 0x6000
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#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
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#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
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#define GSWIP_MDIO_PHY_LINK_UP 0x2000
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#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
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#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
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#define GSWIP_MDIO_PHY_SPEED_M10 0x0000
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#define GSWIP_MDIO_PHY_SPEED_M100 0x0800
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#define GSWIP_MDIO_PHY_SPEED_G1 0x1000
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#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
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#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
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#define GSWIP_MDIO_PHY_FDUP_EN 0x0200
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#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
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#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
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#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
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#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
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#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
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#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
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#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
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#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
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#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
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#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
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#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
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GSWIP_MDIO_PHY_FCONRX_MASK | \
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GSWIP_MDIO_PHY_FCONTX_MASK | \
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GSWIP_MDIO_PHY_LINK_MASK | \
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GSWIP_MDIO_PHY_SPEED_MASK | \
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GSWIP_MDIO_PHY_FDUP_MASK)
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/* GSWIP MII Registers */
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#define GSWIP_MII_CFGp(p) (0x2 * (p))
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#define GSWIP_MII_CFG_RESET BIT(15)
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#define GSWIP_MII_CFG_EN BIT(14)
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#define GSWIP_MII_CFG_ISOLATE BIT(13)
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#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
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#define GSWIP_MII_CFG_RGMII_IBS BIT(8)
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#define GSWIP_MII_CFG_RMII_CLK BIT(7)
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#define GSWIP_MII_CFG_MODE_MIIP 0x0
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#define GSWIP_MII_CFG_MODE_MIIM 0x1
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#define GSWIP_MII_CFG_MODE_RMIIP 0x2
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#define GSWIP_MII_CFG_MODE_RMIIM 0x3
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#define GSWIP_MII_CFG_MODE_RGMII 0x4
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#define GSWIP_MII_CFG_MODE_GMII 0x9
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#define GSWIP_MII_CFG_MODE_MASK 0xf
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#define GSWIP_MII_CFG_RATE_M2P5 0x00
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#define GSWIP_MII_CFG_RATE_M25 0x10
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#define GSWIP_MII_CFG_RATE_M125 0x20
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#define GSWIP_MII_CFG_RATE_M50 0x30
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#define GSWIP_MII_CFG_RATE_AUTO 0x40
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#define GSWIP_MII_CFG_RATE_MASK 0x70
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#define GSWIP_MII_PCDU0 0x01
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#define GSWIP_MII_PCDU1 0x03
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#define GSWIP_MII_PCDU5 0x05
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#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
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#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
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#define GSWIP_MII_PCDU_TXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_TXDLY_MASK)
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#define GSWIP_MII_PCDU_RXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_RXDLY_MASK)
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#define GSWIP_MII_PCDU_RXDLY_DEFAULT 2000 /* picoseconds */
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#define GSWIP_MII_PCDU_TXDLY_DEFAULT 2000 /* picoseconds */
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/* GSWIP Core Registers */
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#define GSWIP_SWRES 0x000
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#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
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#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
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#define GSWIP_VERSION 0x013
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#define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
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#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
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#define GSWIP_VERSION_REV(v) FIELD_GET(GSWIP_VERSION_REV_MASK, v)
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#define GSWIP_VERSION_MOD(v) FIELD_GET(GSWIP_VERSION_MOD_MASK, v)
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#define GSWIP_VERSION_2_0 0x100
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#define GSWIP_VERSION_2_1 0x021
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#define GSWIP_VERSION_2_2 0x122
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#define GSWIP_VERSION_2_2_ETC 0x022
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/* The hardware has the 'major/minor' version bytes in the wrong order
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* preventing numerical comparisons. Swap the bytes of the 16-bit value
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* to end up with REV being the most significant byte and MOD being the
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* least significant byte, which then allows comparing it with the
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* value stored in struct gswip_priv.
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*/
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#define GSWIP_VERSION_GE(priv, ver) ((priv)->version >= swab16(ver))
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#define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
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#define GSWIP_BM_RAM_ADDR 0x044
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#define GSWIP_BM_RAM_CTRL 0x045
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#define GSWIP_BM_RAM_CTRL_BAS BIT(15)
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#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
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#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
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#define GSWIP_BM_QUEUE_GCTRL 0x04A
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#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
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/* buffer management Port Configuration Register */
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#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
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#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
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#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
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/* buffer management Port Control Register */
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#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
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#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
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#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
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/* PCE */
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#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
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#define GSWIP_PCE_TBL_MASK 0x448
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#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
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#define GSWIP_PCE_TBL_ADDR 0x44E
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#define GSWIP_PCE_TBL_CTRL 0x44F
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#define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
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#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
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#define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
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#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
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#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
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#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
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#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
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#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
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#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
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#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
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#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
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#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
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#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
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#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
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#define GSWIP_PCE_GCTRL_0 0x456
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#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
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#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
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#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
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#define GSWIP_PCE_GCTRL_1 0x457
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#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
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#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
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#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
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#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
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#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
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#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
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#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
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#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
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#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
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#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
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#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
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#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
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/* Ethernet Switch PCE Port Control Register 3 */
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#define GSWIP_PCE_PCTRL_3p(p) (0x483 + ((p) * 0xA))
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#define GSWIP_PCE_PCTRL_3_LNDIS BIT(15) /* Learning Disable */
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#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
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#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
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#define GSWIP_PCE_VCTRL_VINR GENMASK(2, 1) /* VLAN Ingress Tag Rule */
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#define GSWIP_PCE_VCTRL_VINR_ALL 0 /* Admit tagged and untagged packets */
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#define GSWIP_PCE_VCTRL_VINR_TAGGED 1 /* Admit only tagged packets */
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#define GSWIP_PCE_VCTRL_VINR_UNTAGGED 2 /* Admit only untagged packets */
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#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
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#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
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#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
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#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
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#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
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#define GSWIP_MAC_FLEN 0x8C5
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#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
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#define GSWIP_MAC_CTRL_0_PADEN BIT(8)
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#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
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#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
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#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
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#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
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#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
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#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
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#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
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#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
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#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
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#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
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#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
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#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
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#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
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#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
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#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
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#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
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#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */
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#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
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#define GSWIP_MAC_CTRL_4p(p) (0x907 + ((p) * 0xC))
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#define GSWIP_MAC_CTRL_4_LPIEN BIT(7) /* LPI Mode Enable */
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#define GSWIP_MAC_CTRL_4_GWAIT_MASK GENMASK(14, 8) /* LPI Wait Time 1G */
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#define GSWIP_MAC_CTRL_4_GWAIT(t) u16_encode_bits((t), GSWIP_MAC_CTRL_4_GWAIT_MASK)
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#define GSWIP_MAC_CTRL_4_WAIT_MASK GENMASK(6, 0) /* LPI Wait Time 100M */
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#define GSWIP_MAC_CTRL_4_WAIT(t) u16_encode_bits((t), GSWIP_MAC_CTRL_4_WAIT_MASK)
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/* Ethernet Switch Fetch DMA Port Control Register */
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#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
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#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
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#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
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#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
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#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
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#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
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#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
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#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
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#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
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/* Ethernet Switch Store DMA Port Control Register */
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#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
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#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
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#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
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#define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
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#define GSWIP_TABLE_ACTIVE_VLAN 0x01
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#define GSWIP_TABLE_VLAN_MAPPING 0x02
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#define GSWIP_TABLE_MAC_BRIDGE 0x0b
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#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */
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#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
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#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
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#define GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID BIT(1) /* Valid bit */
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#define XRX200_GPHY_FW_ALIGN (16 * 1024)
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/* Maximum packet size supported by the switch. In theory this should be 10240,
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* but long packets currently cause lock-ups with an MTU of over 2526. Medium
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* packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
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* over 2526), hence an MTU value of 2400 seems safe. This issue only affects
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* packet reception. This is probably caused by the PPA engine, which is on the
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* RX part of the device. Packet transmission works properly up to 10240.
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*/
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#define GSWIP_MAX_PACKET_LENGTH 2400
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#define GSWIP_VLAN_UNAWARE_PVID 0
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struct gswip_pce_microcode {
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u16 val_3;
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u16 val_2;
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u16 val_1;
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u16 val_0;
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};
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struct gswip_hw_info {
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int max_ports;
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unsigned int allowed_cpu_ports;
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unsigned int mii_ports;
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int mii_port_reg_offset;
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bool supports_2500m;
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const struct gswip_pce_microcode (*pce_microcode)[];
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size_t pce_microcode_size;
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enum dsa_tag_protocol tag_protocol;
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void (*phylink_get_caps)(struct dsa_switch *ds, int port,
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struct phylink_config *config);
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struct phylink_pcs *(*mac_select_pcs)(struct phylink_config *config,
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phy_interface_t interface);
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};
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struct gswip_gphy_fw {
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struct clk *clk_gate;
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struct reset_control *reset;
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u32 fw_addr_offset;
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char *fw_name;
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};
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struct gswip_vlan {
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struct net_device *bridge;
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u16 vid;
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u8 fid;
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};
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struct gswip_priv {
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struct regmap *gswip;
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struct regmap *mdio;
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struct regmap *mii;
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const struct gswip_hw_info *hw_info;
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const struct xway_gphy_match_data *gphy_fw_name_cfg;
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struct dsa_switch *ds;
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struct device *dev;
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struct regmap *rcu_regmap;
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struct gswip_vlan vlans[64];
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int num_gphy_fw;
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struct gswip_gphy_fw *gphy_fw;
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struct mutex pce_table_lock;
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u16 version;
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};
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int gswip_probe_common(struct gswip_priv *priv, u32 version);
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#endif /* __LANTIQ_GSWIP_H */
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