Kefeng Wang 9fe57d8c57 riscv: Fix undefined reference to vmemmap_populate_basepages ...

Using CONFIG_SPARSEMEM_VMEMMAP instead of CONFIG_SPARSEMEM to fix
following build issue.

  riscv64-linux-ld: arch/riscv/mm/init.o: in function 'vmemmap_populate':
  init.c:(.meminit.text+0x8): undefined reference to 'vmemmap_populate_basepages'

Cc: Logan Gunthorpe <logang@deltatee.com>
Fixes: d95f1a542c ("RISC-V: Implement sparsemem")
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

2019-10-23 14:53:46 -07:00

..

cacheflush.c

riscv: cleanup riscv_cpuid_to_hartid_mask

2019-09-05 01:51:57 -07:00

context.c

riscv: Using CSR numbers to access CSRs

2019-08-30 11:04:19 -07:00

extable.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120

2019-05-24 17:39:02 +02:00

fault.c

Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace

2019-07-08 21:48:15 -07:00

hugetlbpage.c

riscv: Introduce huge page support for 32/64bit kernel

2019-07-03 15:23:38 -07:00

init.c

riscv: Fix undefined reference to vmemmap_populate_basepages

2019-10-23 14:53:46 -07:00

ioremap.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

Makefile

riscv: move the TLB flush logic out of line

2019-09-05 01:54:51 -07:00

sifive_l2_cache.c

riscv: ccache: Remove unused variable

2019-07-04 03:12:24 -07:00

tlbflush.c

riscv: move the TLB flush logic out of line

2019-09-05 01:54:51 -07:00