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i.MX51 only has 3 UARTs and no CCGR7 register. In place of the CCGR7 register on i.MX50/i.MX53 that contains the ipg and per clock gates for UARTs 4 and 5, on i.MX51 there is the CMEOR register. Without this patch, the code disabling the UART clocks would also clear the mod_en_ov_vpu bit in the CMEOR register, among others, which causes register accesses to the VPU to lock up the system. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>