Ashutosh Dixit f76646c83f drm/xe: Label RING_CONTEXT_CONTROL as masked ...

RING_CONTEXT_CONTROL is a masked register.

v2: Also clean up setting register value (Lucas)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240404161256.3852502-1-ashutosh.dixit@intel.com
(cherry picked from commit dc30c6e714)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

2024-04-11 08:41:54 -05:00

..

xe_engine_regs.h

drm/xe: Label RING_CONTEXT_CONTROL as masked

2024-04-11 08:41:54 -05:00

xe_gpu_commands.h

drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLT

2023-12-21 11:46:15 -05:00

xe_gsc_regs.h

drm/xe/huc: Prepare for 2-step HuC authentication

2023-12-21 11:45:24 -05:00

xe_gt_regs.h

drm/xe/hwmon: Refactor xe hwmon

2024-02-06 08:42:03 -05:00

xe_guc_regs.h

drm/xe: explicitly set GGTT access for GuC DMA

2023-12-21 11:45:07 -05:00

xe_lrc_layout.h

drm/xe: Update LRC context layout definitions

2023-12-21 16:31:29 -05:00

xe_mchbar_regs.h

drm/xe/hwmon: Expose power1_max_interval

2023-12-21 11:43:32 -05:00

xe_pcode_regs.h

drm/xe/hwmon: Refactor xe hwmon

2024-02-06 08:42:03 -05:00

xe_reg_defs.h

drm/xe: Expand XE_REG_OPTION_MASKED documentation

2023-12-21 11:45:23 -05:00

xe_regs.h

drm/xe: Define interrupt vector bits with the interrupt registers

2023-12-21 11:46:16 -05:00

xe_sriov_regs.h

drm/xe/pf: Introduce Local Memory Translation Table

2023-12-21 11:45:27 -05:00