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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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5f5598d945
Each memory client has unique hardware ID, add these IDs. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
153 lines
4.7 KiB
C
153 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_AFI 3
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#define TEGRA_SWGROUP_AVPC 4
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#define TEGRA_SWGROUP_HDA 5
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#define TEGRA_SWGROUP_HC 6
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#define TEGRA_SWGROUP_NVENC 7
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#define TEGRA_SWGROUP_PPCS 8
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#define TEGRA_SWGROUP_SATA 9
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#define TEGRA_SWGROUP_MPCORE 10
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#define TEGRA_SWGROUP_ISP2 11
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#define TEGRA_SWGROUP_XUSB_HOST 12
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#define TEGRA_SWGROUP_XUSB_DEV 13
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#define TEGRA_SWGROUP_ISP2B 14
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#define TEGRA_SWGROUP_TSEC 15
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#define TEGRA_SWGROUP_A9AVP 16
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#define TEGRA_SWGROUP_GPU 17
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#define TEGRA_SWGROUP_SDMMC1A 18
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#define TEGRA_SWGROUP_SDMMC2A 19
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#define TEGRA_SWGROUP_SDMMC3A 20
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#define TEGRA_SWGROUP_SDMMC4A 21
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#define TEGRA_SWGROUP_VIC 22
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#define TEGRA_SWGROUP_VI 23
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#define TEGRA_SWGROUP_NVDEC 24
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#define TEGRA_SWGROUP_APE 25
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#define TEGRA_SWGROUP_NVJPG 26
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#define TEGRA_SWGROUP_SE 27
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#define TEGRA_SWGROUP_AXIAP 28
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#define TEGRA_SWGROUP_ETR 29
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#define TEGRA_SWGROUP_TSECB 30
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#define TEGRA_SWGROUP_NV 31
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#define TEGRA_SWGROUP_NV2 32
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#define TEGRA_SWGROUP_PPCS1 33
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#define TEGRA_SWGROUP_DC1 34
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#define TEGRA_SWGROUP_PPCS2 35
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#define TEGRA_SWGROUP_HC1 36
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#define TEGRA_SWGROUP_SE1 37
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#define TEGRA_SWGROUP_TSEC1 38
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#define TEGRA_SWGROUP_TSECB1 39
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#define TEGRA_SWGROUP_NVDEC1 40
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#define TEGRA210_MC_RESET_AFI 0
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#define TEGRA210_MC_RESET_AVPC 1
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#define TEGRA210_MC_RESET_DC 2
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#define TEGRA210_MC_RESET_DCB 3
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#define TEGRA210_MC_RESET_HC 4
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#define TEGRA210_MC_RESET_HDA 5
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#define TEGRA210_MC_RESET_ISP2 6
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#define TEGRA210_MC_RESET_MPCORE 7
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#define TEGRA210_MC_RESET_NVENC 8
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#define TEGRA210_MC_RESET_PPCS 9
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#define TEGRA210_MC_RESET_SATA 10
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#define TEGRA210_MC_RESET_VI 11
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#define TEGRA210_MC_RESET_VIC 12
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#define TEGRA210_MC_RESET_XUSB_HOST 13
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#define TEGRA210_MC_RESET_XUSB_DEV 14
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#define TEGRA210_MC_RESET_A9AVP 15
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#define TEGRA210_MC_RESET_TSEC 16
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#define TEGRA210_MC_RESET_SDMMC1 17
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#define TEGRA210_MC_RESET_SDMMC2 18
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#define TEGRA210_MC_RESET_SDMMC3 19
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#define TEGRA210_MC_RESET_SDMMC4 20
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#define TEGRA210_MC_RESET_ISP2B 21
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#define TEGRA210_MC_RESET_GPU 22
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#define TEGRA210_MC_RESET_NVDEC 23
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#define TEGRA210_MC_RESET_APE 24
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#define TEGRA210_MC_RESET_SE 25
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#define TEGRA210_MC_RESET_NVJPG 26
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#define TEGRA210_MC_RESET_AXIAP 27
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#define TEGRA210_MC_RESET_ETR 28
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#define TEGRA210_MC_RESET_TSECB 29
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#define TEGRA210_MC_PTCR 0
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#define TEGRA210_MC_DISPLAY0A 1
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#define TEGRA210_MC_DISPLAY0AB 2
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#define TEGRA210_MC_DISPLAY0B 3
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#define TEGRA210_MC_DISPLAY0BB 4
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#define TEGRA210_MC_DISPLAY0C 5
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#define TEGRA210_MC_DISPLAY0CB 6
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#define TEGRA210_MC_AFIR 14
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#define TEGRA210_MC_AVPCARM7R 15
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#define TEGRA210_MC_DISPLAYHC 16
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#define TEGRA210_MC_DISPLAYHCB 17
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#define TEGRA210_MC_HDAR 21
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#define TEGRA210_MC_HOST1XDMAR 22
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#define TEGRA210_MC_HOST1XR 23
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#define TEGRA210_MC_NVENCSRD 28
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#define TEGRA210_MC_PPCSAHBDMAR 29
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#define TEGRA210_MC_PPCSAHBSLVR 30
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#define TEGRA210_MC_SATAR 31
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#define TEGRA210_MC_MPCORER 39
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#define TEGRA210_MC_NVENCSWR 43
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#define TEGRA210_MC_AFIW 49
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#define TEGRA210_MC_AVPCARM7W 50
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#define TEGRA210_MC_HDAW 53
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#define TEGRA210_MC_HOST1XW 54
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#define TEGRA210_MC_MPCOREW 57
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#define TEGRA210_MC_PPCSAHBDMAW 59
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#define TEGRA210_MC_PPCSAHBSLVW 60
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#define TEGRA210_MC_SATAW 61
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#define TEGRA210_MC_ISPRA 68
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#define TEGRA210_MC_ISPWA 70
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#define TEGRA210_MC_ISPWB 71
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#define TEGRA210_MC_XUSB_HOSTR 74
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#define TEGRA210_MC_XUSB_HOSTW 75
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#define TEGRA210_MC_XUSB_DEVR 76
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#define TEGRA210_MC_XUSB_DEVW 77
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#define TEGRA210_MC_ISPRAB 78
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#define TEGRA210_MC_ISPWAB 80
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#define TEGRA210_MC_ISPWBB 81
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#define TEGRA210_MC_TSECSRD 84
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#define TEGRA210_MC_TSECSWR 85
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#define TEGRA210_MC_A9AVPSCR 86
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#define TEGRA210_MC_A9AVPSCW 87
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#define TEGRA210_MC_GPUSRD 88
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#define TEGRA210_MC_GPUSWR 89
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#define TEGRA210_MC_DISPLAYT 90
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#define TEGRA210_MC_SDMMCRA 96
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#define TEGRA210_MC_SDMMCRAA 97
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#define TEGRA210_MC_SDMMCR 98
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#define TEGRA210_MC_SDMMCRAB 99
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#define TEGRA210_MC_SDMMCWA 100
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#define TEGRA210_MC_SDMMCWAA 101
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#define TEGRA210_MC_SDMMCW 102
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#define TEGRA210_MC_SDMMCWAB 103
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#define TEGRA210_MC_VICSRD 108
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#define TEGRA210_MC_VICSWR 109
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#define TEGRA210_MC_VIW 114
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#define TEGRA210_MC_DISPLAYD 115
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#define TEGRA210_MC_NVDECSRD 120
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#define TEGRA210_MC_NVDECSWR 121
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#define TEGRA210_MC_APER 122
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#define TEGRA210_MC_APEW 123
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#define TEGRA210_MC_NVJPGRD 126
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#define TEGRA210_MC_NVJPGWR 127
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#define TEGRA210_MC_SESRD 128
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#define TEGRA210_MC_SESWR 129
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#define TEGRA210_MC_AXIAPR 130
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#define TEGRA210_MC_AXIAPW 131
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#define TEGRA210_MC_ETRR 132
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#define TEGRA210_MC_ETRW 133
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#define TEGRA210_MC_TSECSRDB 134
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#define TEGRA210_MC_TSECSWRB 135
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#define TEGRA210_MC_GPUSRD2 136
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#define TEGRA210_MC_GPUSWR2 137
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#endif
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