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11016c795e
The RDMA device needs information of controller memory bar and doorbell capability to share with user context. Discover CMB regions and express doorbell capabilities on device init. Reviewed-by: Shannon Nelson <shannon.nelson@amd.com> Co-developed-by: Pablo Cascón <pablo.cascon@amd.com> Signed-off-by: Pablo Cascón <pablo.cascon@amd.com> Co-developed-by: Allen Hubbe <allen.hubbe@amd.com> Signed-off-by: Allen Hubbe <allen.hubbe@amd.com> Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com> Link: https://patch.msgid.link/20250903061606.4139957-7-abhijit.gangurde@amd.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
132 lines
3.8 KiB
C
132 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */
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#ifndef _IONIC_API_H_
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#define _IONIC_API_H_
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#include <linux/auxiliary_bus.h>
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#include "ionic_if.h"
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#include "ionic_regs.h"
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/**
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* struct ionic_aux_dev - Auxiliary device information
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* @lif: Logical interface
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* @idx: Index identifier
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* @adev: Auxiliary device
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*/
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struct ionic_aux_dev {
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struct ionic_lif *lif;
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int idx;
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struct auxiliary_device adev;
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};
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/**
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* struct ionic_admin_ctx - Admin command context
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* @work: Work completion wait queue element
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* @cmd: Admin command (64B) to be copied to the queue
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* @comp: Admin completion (16B) copied from the queue
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*/
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struct ionic_admin_ctx {
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struct completion work;
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union ionic_adminq_cmd cmd;
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union ionic_adminq_comp comp;
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};
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#define IONIC_INTR_INDEX_NOT_ASSIGNED -1
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#define IONIC_INTR_NAME_MAX_SZ 32
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/**
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* struct ionic_intr_info - Interrupt information
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* @name: Name identifier
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* @rearm_count: Interrupt rearm count
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* @index: Interrupt index position
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* @vector: Interrupt number
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* @dim_coal_hw: Interrupt coalesce value in hardware units
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* @affinity_mask: CPU affinity mask
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* @aff_notify: context for notification of IRQ affinity changes
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*/
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struct ionic_intr_info {
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char name[IONIC_INTR_NAME_MAX_SZ];
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u64 rearm_count;
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unsigned int index;
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unsigned int vector;
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u32 dim_coal_hw;
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cpumask_var_t *affinity_mask;
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struct irq_affinity_notify aff_notify;
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};
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/**
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* ionic_adminq_post_wait - Post an admin command and wait for response
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* @lif: Logical interface
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* @ctx: API admin command context
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*
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* Post the command to an admin queue in the ethernet driver. If this command
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* succeeds, then the command has been posted, but that does not indicate a
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* completion. If this command returns success, then the completion callback
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* will eventually be called.
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*
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* Return: zero or negative error status
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*/
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int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx);
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/**
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* ionic_error_to_errno - Transform ionic_if errors to os errno
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* @code: Ionic error number
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*
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* Return: Negative OS error number or zero
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*/
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int ionic_error_to_errno(enum ionic_status_code code);
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/**
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* ionic_request_rdma_reset - request reset or disable the device or lif
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* @lif: Logical interface
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*
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* The reset is triggered asynchronously. It will wait until reset request
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* completes or times out.
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*/
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void ionic_request_rdma_reset(struct ionic_lif *lif);
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/**
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* ionic_intr_alloc - Reserve a device interrupt
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* @lif: Logical interface
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* @intr: Reserved ionic interrupt structure
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*
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* Reserve an interrupt index and get irq number for that index.
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*
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* Return: zero or negative error status
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*/
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int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr);
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/**
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* ionic_intr_free - Release a device interrupt index
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* @lif: Logical interface
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* @intr: Interrupt index
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*
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* Mark the interrupt index unused so that it can be reserved again.
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*/
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void ionic_intr_free(struct ionic_lif *lif, int intr);
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/**
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* ionic_get_cmb - Reserve cmb pages
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* @lif: Logical interface
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* @pgid: First page index
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* @pgaddr: First page bus addr (contiguous)
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* @order: Log base two number of pages (PAGE_SIZE)
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* @stride_log2: Size of stride to determine CMB pool
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* @expdb: Will be set to true if this CMB region has expdb enabled
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*
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* Return: zero or negative error status
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*/
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int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr,
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int order, u8 stride_log2, bool *expdb);
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/**
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* ionic_put_cmb - Release cmb pages
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* @lif: Logical interface
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* @pgid: First page index
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* @order: Log base two number of pages (PAGE_SIZE)
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*/
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void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);
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#endif /* _IONIC_API_H_ */
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