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e617f3a370
Falcon engines have two distinct register bases: `PFALCON` and `PFALCON2`. So far we assumed that `PFALCON2` was located at `PFALCON + 0x1000` because that is the case of most engines, but there are exceptions (NVDEC uses `0x1c00`). Fix this shortcoming by leveraging the redesigned relative registers definitions to assign a distinct `PFalcon2Base` base address to each falcon engine. Reviewed-by: Lyude Paul <lyude@redhat.com> Link: https://lore.kernel.org/r/20250718-nova-regs-v2-16-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
33 lines
847 B
Rust
33 lines
847 B
Rust
// SPDX-License-Identifier: GPL-2.0
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use crate::{
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driver::Bar0,
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falcon::{Falcon, FalconEngine, PFalcon2Base, PFalconBase},
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regs::{self, macros::RegisterBase},
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};
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/// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
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pub(crate) struct Gsp(());
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impl RegisterBase<PFalconBase> for Gsp {
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const BASE: usize = 0x00110000;
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}
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impl RegisterBase<PFalcon2Base> for Gsp {
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const BASE: usize = 0x00111000;
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}
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impl FalconEngine for Gsp {
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const ID: Self = Gsp(());
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}
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impl Falcon<Gsp> {
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/// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to
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/// allow GSP to signal CPU for processing new messages in message queue.
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pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) {
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regs::NV_PFALCON_FALCON_IRQSCLR::default()
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.set_swgen0(true)
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.write(bar, &Gsp::ID);
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}
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}
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