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9aa12167ef
Recent changes require the raw folio flags to be accessed via ".f". The
merge commit introducing this change adapted most architecture code but
forgot the csky abiv2.
[rppt@kernel.org: add fix for arch/csky/abiv2/cacheflush.c]
Link: https://lkml.kernel.org/r/aPCE238oxAB9QcZa@kernel.org
Fixes: 53fbef56e0 ("mm: introduce memdesc_flags_t")
Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de>
Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Acked-by: Zi Yan <ziy@nvidia.com>
Cc: Guo Ren <guoren@kernel.org>
Cc: Matthew Wilcox (Oracle) <willy@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
93 lines
2.2 KiB
C
93 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/cache.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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#include <asm/tlbflush.h>
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void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
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unsigned long address, pte_t *pte, unsigned int nr)
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{
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unsigned long pfn = pte_pfn(*pte);
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struct folio *folio;
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unsigned int i;
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flush_tlb_page(vma, address);
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if (!pfn_valid(pfn))
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return;
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folio = page_folio(pfn_to_page(pfn));
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if (test_and_set_bit(PG_dcache_clean, &folio->flags.f))
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return;
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icache_inv_range(address, address + nr*PAGE_SIZE);
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for (i = 0; i < folio_nr_pages(folio); i++) {
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unsigned long addr = (unsigned long) kmap_local_folio(folio,
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i * PAGE_SIZE);
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dcache_wb_range(addr, addr + PAGE_SIZE);
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if (vma->vm_flags & VM_EXEC)
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icache_inv_range(addr, addr + PAGE_SIZE);
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kunmap_local((void *) addr);
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}
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}
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void flush_icache_deferred(struct mm_struct *mm)
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{
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unsigned int cpu = smp_processor_id();
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cpumask_t *mask = &mm->context.icache_stale_mask;
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if (cpumask_test_cpu(cpu, mask)) {
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cpumask_clear_cpu(cpu, mask);
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/*
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* Ensure the remote hart's writes are visible to this hart.
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* This pairs with a barrier in flush_icache_mm.
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*/
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smp_mb();
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local_icache_inv_all(NULL);
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}
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}
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void flush_icache_mm_range(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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#ifdef CONFIG_CPU_HAS_ICACHE_INS
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if (mm == current->mm) {
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icache_inv_range(start, end);
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preempt_enable();
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return;
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}
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#endif
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_icache_inv_all(NULL);
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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if (mm != current->active_mm || !cpumask_empty(&others)) {
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on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1);
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cpumask_clear(mask);
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}
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preempt_enable();
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}
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