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By default, the UFS controller allocates a fixed number of RX and TX engines statically. Consequently, when UFS reads are in progress, the TX ICE engines remain idle, and vice versa. This leads to inefficient utilization of RX and TX engines. To address this limitation, enable the UFS shared ICE feature for Qualcomm UFS V5.0 and above. This feature utilizes a pool of crypto cores for both TX streams (UFS Write – Encryption) and RX streams (UFS Read – Decryption). With this approach, crypto cores are dynamically allocated to either the RX or TX stream as needed. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> Link: https://lore.kernel.org/r/20250203112739.11425-1-quic_rdwivedi@quicinc.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>