Files
linux/drivers
Icenowy Zheng 62d212bdb0 clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.

Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.

Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-09-17 12:03:08 +02:00
..
2017-09-14 17:34:43 +02:00
2017-08-29 13:46:35 +02:00
2017-08-22 11:04:51 -07:00
2017-08-30 14:03:42 -06:00
2017-08-24 09:57:28 +02:00