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01f96b8125
For some coresight components like CTI and TPDM, there could be numerous of them. From the node name, we can only get the type and register address of the component. We can't identify the HW or the system the component belongs to. Add label sysfs node support for showing the intuitive name of the device. Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20250816072529.3716968-3-quic_jinlmao@quicinc.com
281 lines
10 KiB
Plaintext
281 lines
10 KiB
Plaintext
What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
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Date: January 2023
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KernelVersion: 6.2
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Run integration test for tpdm. Integration test
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will generate test data for tpdm. It can help to make
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sure that the trace path is enabled and the link configurations
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are fine.
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Accepts only one of the 2 values - 1 or 2.
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1 : Generate 64 bits data
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2 : Generate 32 bits data
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What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Reset the dataset of the tpdm.
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Accepts only one value - 1.
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1 : Reset the dataset of the tpdm
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger type of the DSB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB trigger type to false
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1 : Set the DSB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger timestamp of the DSB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB trigger type to false
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1 : Set the DSB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the programming mode of the DSB for tpdm.
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Accepts the value needs to be greater than 0. What data
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bits do is listed below.
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Bit[0:1] : Test mode control bit for choosing the inputs.
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Bit[3] : Set to 0 for low performance mode. Set to 1 for high
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performance mode.
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Bit[4:8] : Select byte lane for high performance mode.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the index number of the edge detection for the DSB
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subunit TPDM. Since there are at most 256 edge detections, this
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value ranges from 0 to 255.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Write a data to control the edge detection corresponding to
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the index number. Before writing data to this sysfs file,
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"ctrl_idx" should be written first to configure the index
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number of the edge detection which needs to be controlled.
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Accepts only one of the following values.
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0 - Rising edge detection
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1 - Falling edge detection
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2 - Rising and falling edge detection (toggle detection)
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Write a data to mask the edge detection corresponding to the index
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number. Before writing data to this sysfs file, "ctrl_idx" should
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be written first to configure the index number of the edge detection
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which needs to be masked.
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Accepts only one of the 2 values - 0 or 1.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Read a set of the edge control value of the DSB in TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Read a set of the edge control mask of the DSB in TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the trigger pattern for the DSB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the trigger pattern for the DSB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Set the pattern timestamp of DSB tpdm. Read
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the pattern timestamp of DSB tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Disable DSB pattern timestamp.
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1 : Enable DSB pattern timestamp.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Set the pattern type of DSB tpdm. Read
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the pattern type of DSB tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB pattern type to value.
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1 : Set the DSB pattern type to toggle.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
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Date: March 2023
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KernelVersion: 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the MSR(mux select register) for the DSB subunit
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TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description: (Write) Set the data collection mode of CMB tpdm. Continuous
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change creates CMB data set elements on every CMBCLK edge.
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Trace-on-change creates CMB data set elements only when a new
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data set element differs in value from the previous element
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in a CMB data set.
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Accepts only one of the 2 values - 0 or 1.
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0 : Continuous CMB collection mode.
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1 : Trace-on-change CMB collection mode.
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1]
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the trigger pattern for the CMB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1]
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the trigger pattern for the CMB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1]
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the pattern for the CMB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1]
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the pattern for the CMB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Set the pattern timestamp of CMB tpdm. Read
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the pattern timestamp of CMB tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Disable CMB pattern timestamp.
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1 : Enable CMB pattern timestamp.
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger timestamp of the CMB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the CMB trigger type to false
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1 : Set the CMB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Read or write the status of timestamp upon all interface.
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Only value 0 and 1 can be written to this node. Set this node to 1 to request
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timestamp to all trace packet.
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Accepts only one of the 2 values - 0 or 1.
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0 : Disable the timestamp of all trace packets.
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1 : Enable the timestamp of all trace packets.
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What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
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Date: January 2024
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KernelVersion: 6.9
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the MSR(mux select register) for the CMB subunit
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TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane
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Date: Feb 2025
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KernelVersion 6.15
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get which lane participates in the output pattern
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match cross trigger mechanism for the MCMB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select
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Date: Feb 2025
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KernelVersion 6.15
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the enablement of the individual lane.
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What: /sys/bus/coresight/devices/<tpdm-name>/label
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Date: Aug 2025
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KernelVersion 6.18
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Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
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Description: (Read) Show hardware context information of device.
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