Files
linux/drivers
Paul Cercueil 568b9de48d clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.

This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.

Restore the correct behaviour using the newly introduced .div_table
field.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20190701113606.4130-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 14:33:39 -07:00
..
2019-07-18 09:49:30 +02:00
2019-07-18 09:49:30 +02:00
2019-07-15 09:42:32 -07:00
2019-07-15 09:20:27 -03:00