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The Glymur USB subsystem contains three USB 3.2 Gen 2 controllers, one USB 3.2 multi-port controller, and one USB 2.0-only controller. This includes five SS USB QMP PHYs (three combo and two UNI) and six M31 eUSB2 PHYs. All controllers are based on SNPS DWC3, so describe them as Qualcomm flattened DWC3 nodes. Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260320-dts-qcom-glymur-add-usb-support-v7-1-ba367eda6010@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>