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11e15a6f32
As like other SDX targets, SDX75 QPIC BCM resource is also modeled as a
RPMh clock in clk-rpmh driver. However, for SDX75, this resource was also
described as an interconnect node mistakenly.
Hence, drop the QPIC interconnect IDs and let the clients use clk-rpmh
driver to vote for this resource.
Even though this change is an ABI break, it is necessary to avoid
describing the same resource provider in two different drivers, as it may
lead to votes from clients overriding each other.
Fixes: 956329ec7c ("dt-bindings: interconnect: Add compatibles for SDX75")
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
[mani: kept the QUP defines value unchanged]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-2-20d6820e455c@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
101 lines
2.6 KiB
C
101 lines
2.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
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#define MASTER_QUP_CORE_0 1
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#define SLAVE_QUP_CORE_0 3
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_CNOC_DC_NOC 0
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#define SLAVE_LAGG_CFG 1
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#define SLAVE_MCCC_MASTER 2
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#define SLAVE_GEM_NOC_CFG 3
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#define SLAVE_SNOOP_BWMON 4
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#define MASTER_SYS_TCU 0
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#define MASTER_APPSS_PROC 1
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#define MASTER_GEM_NOC_CFG 2
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#define MASTER_MSS_PROC 3
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#define MASTER_ANOC_PCIE_GEM_NOC 4
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#define MASTER_SNOC_SF_MEM_NOC 5
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#define MASTER_GIC 6
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#define MASTER_IPA_PCIE 7
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#define SLAVE_GEM_NOC_CNOC 8
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#define SLAVE_LLCC 9
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#define SLAVE_MEM_NOC_PCIE_SNOC 10
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#define SLAVE_SERVICE_GEM_NOC 11
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#define MASTER_PCIE_0 0
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#define MASTER_PCIE_1 1
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#define MASTER_PCIE_2 2
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#define SLAVE_ANOC_PCIE_GEM_NOC 3
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#define MASTER_AUDIO 0
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#define MASTER_GIC_AHB 1
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#define MASTER_PCIE_RSCC 2
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#define MASTER_QDSS_BAM 3
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#define MASTER_QPIC 4
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#define MASTER_QUP_0 5
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#define MASTER_ANOC_SNOC 6
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#define MASTER_GEM_NOC_CNOC 7
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#define MASTER_GEM_NOC_PCIE_SNOC 8
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#define MASTER_SNOC_CFG 9
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#define MASTER_PCIE_ANOC_CFG 10
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#define MASTER_CRYPTO 11
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#define MASTER_IPA 12
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#define MASTER_MVMSS 13
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#define MASTER_EMAC_0 14
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#define MASTER_EMAC_1 15
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#define MASTER_QDSS_ETR 16
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#define MASTER_QDSS_ETR_1 17
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#define MASTER_SDCC_1 18
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#define MASTER_SDCC_4 19
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#define MASTER_USB3_0 20
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#define SLAVE_ETH0_CFG 21
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#define SLAVE_ETH1_CFG 22
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#define SLAVE_AUDIO 23
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#define SLAVE_CLK_CTL 24
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#define SLAVE_CRYPTO_0_CFG 25
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#define SLAVE_IMEM_CFG 26
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#define SLAVE_IPA_CFG 27
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#define SLAVE_IPC_ROUTER_CFG 28
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#define SLAVE_CNOC_MSS 29
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#define SLAVE_ICBDI_MVMSS_CFG 30
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#define SLAVE_PCIE_0_CFG 31
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#define SLAVE_PCIE_1_CFG 32
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#define SLAVE_PCIE_2_CFG 33
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#define SLAVE_PCIE_RSC_CFG 34
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#define SLAVE_PDM 35
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#define SLAVE_PRNG 36
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#define SLAVE_QDSS_CFG 37
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#define SLAVE_QPIC 38
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#define SLAVE_QUP_0 39
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#define SLAVE_SDCC_1 40
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#define SLAVE_SDCC_4 41
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#define SLAVE_SPMI_VGI_COEX 42
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#define SLAVE_TCSR 43
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#define SLAVE_TLMM 44
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#define SLAVE_USB3 45
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#define SLAVE_USB3_PHY_CFG 46
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#define SLAVE_A1NOC_CFG 47
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#define SLAVE_DDRSS_CFG 48
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#define SLAVE_SNOC_GEM_NOC_SF 49
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#define SLAVE_SNOC_CFG 50
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#define SLAVE_PCIE_ANOC_CFG 51
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#define SLAVE_IMEM 52
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#define SLAVE_SERVICE_PCIE_ANOC 53
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#define SLAVE_SERVICE_SNOC 54
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#define SLAVE_PCIE_0 55
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#define SLAVE_PCIE_1 56
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#define SLAVE_PCIE_2 57
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#define SLAVE_QDSS_STM 58
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#define SLAVE_TCU 59
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#endif
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