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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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e0b5cfc316
The KVM ISA extension related checks are not VCPU specific and should be factored out of vcpu_onereg.c into separate sources. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Reviewed-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260120080013.2153519-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
254 lines
6.8 KiB
C
254 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2026 Qualcomm Technologies, Inc.
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*/
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#include <linux/cpufeature.h>
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#include <linux/errno.h>
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#include <linux/kvm_host.h>
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#include <linux/nospec.h>
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#include <linux/pgtable.h>
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#include <asm/kvm_isa.h>
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#include <asm/vector.h>
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#define KVM_ISA_EXT_ARR(ext) \
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[KVM_RISCV_ISA_EXT_##ext] = RISCV_ISA_EXT_##ext
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/* Mapping between KVM ISA Extension ID & guest ISA extension ID */
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static const unsigned long kvm_isa_ext_arr[] = {
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/* Single letter extensions (alphabetically sorted) */
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[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
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[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
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[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
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[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
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[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
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[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
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[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
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[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
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/* Multi letter extensions (alphabetically sorted) */
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KVM_ISA_EXT_ARR(SMNPM),
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KVM_ISA_EXT_ARR(SMSTATEEN),
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KVM_ISA_EXT_ARR(SSAIA),
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KVM_ISA_EXT_ARR(SSCOFPMF),
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KVM_ISA_EXT_ARR(SSNPM),
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KVM_ISA_EXT_ARR(SSTC),
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KVM_ISA_EXT_ARR(SVADE),
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KVM_ISA_EXT_ARR(SVADU),
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KVM_ISA_EXT_ARR(SVINVAL),
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KVM_ISA_EXT_ARR(SVNAPOT),
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KVM_ISA_EXT_ARR(SVPBMT),
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KVM_ISA_EXT_ARR(SVVPTC),
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KVM_ISA_EXT_ARR(ZAAMO),
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KVM_ISA_EXT_ARR(ZABHA),
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KVM_ISA_EXT_ARR(ZACAS),
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KVM_ISA_EXT_ARR(ZALASR),
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KVM_ISA_EXT_ARR(ZALRSC),
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KVM_ISA_EXT_ARR(ZAWRS),
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KVM_ISA_EXT_ARR(ZBA),
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KVM_ISA_EXT_ARR(ZBB),
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KVM_ISA_EXT_ARR(ZBC),
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KVM_ISA_EXT_ARR(ZBKB),
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KVM_ISA_EXT_ARR(ZBKC),
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KVM_ISA_EXT_ARR(ZBKX),
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KVM_ISA_EXT_ARR(ZBS),
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KVM_ISA_EXT_ARR(ZCA),
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KVM_ISA_EXT_ARR(ZCB),
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KVM_ISA_EXT_ARR(ZCD),
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KVM_ISA_EXT_ARR(ZCF),
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KVM_ISA_EXT_ARR(ZCLSD),
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KVM_ISA_EXT_ARR(ZCMOP),
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KVM_ISA_EXT_ARR(ZFA),
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KVM_ISA_EXT_ARR(ZFBFMIN),
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KVM_ISA_EXT_ARR(ZFH),
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KVM_ISA_EXT_ARR(ZFHMIN),
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KVM_ISA_EXT_ARR(ZICBOM),
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KVM_ISA_EXT_ARR(ZICBOP),
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KVM_ISA_EXT_ARR(ZICBOZ),
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KVM_ISA_EXT_ARR(ZICCRSE),
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KVM_ISA_EXT_ARR(ZICNTR),
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KVM_ISA_EXT_ARR(ZICOND),
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KVM_ISA_EXT_ARR(ZICSR),
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KVM_ISA_EXT_ARR(ZIFENCEI),
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KVM_ISA_EXT_ARR(ZIHINTNTL),
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KVM_ISA_EXT_ARR(ZIHINTPAUSE),
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KVM_ISA_EXT_ARR(ZIHPM),
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KVM_ISA_EXT_ARR(ZILSD),
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KVM_ISA_EXT_ARR(ZIMOP),
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KVM_ISA_EXT_ARR(ZKND),
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KVM_ISA_EXT_ARR(ZKNE),
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KVM_ISA_EXT_ARR(ZKNH),
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KVM_ISA_EXT_ARR(ZKR),
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KVM_ISA_EXT_ARR(ZKSED),
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KVM_ISA_EXT_ARR(ZKSH),
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KVM_ISA_EXT_ARR(ZKT),
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KVM_ISA_EXT_ARR(ZTSO),
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KVM_ISA_EXT_ARR(ZVBB),
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KVM_ISA_EXT_ARR(ZVBC),
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KVM_ISA_EXT_ARR(ZVFBFMIN),
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KVM_ISA_EXT_ARR(ZVFBFWMA),
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KVM_ISA_EXT_ARR(ZVFH),
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KVM_ISA_EXT_ARR(ZVFHMIN),
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KVM_ISA_EXT_ARR(ZVKB),
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KVM_ISA_EXT_ARR(ZVKG),
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KVM_ISA_EXT_ARR(ZVKNED),
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KVM_ISA_EXT_ARR(ZVKNHA),
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KVM_ISA_EXT_ARR(ZVKNHB),
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KVM_ISA_EXT_ARR(ZVKSED),
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KVM_ISA_EXT_ARR(ZVKSH),
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KVM_ISA_EXT_ARR(ZVKT),
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};
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unsigned long kvm_riscv_base2isa_ext(unsigned long base_ext)
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{
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unsigned long i;
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for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
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if (kvm_isa_ext_arr[i] == base_ext)
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return i;
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}
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return KVM_RISCV_ISA_EXT_MAX;
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}
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int __kvm_riscv_isa_check_host(unsigned long kvm_ext, unsigned long *base_ext)
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{
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unsigned long host_ext;
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if (kvm_ext >= KVM_RISCV_ISA_EXT_MAX ||
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kvm_ext >= ARRAY_SIZE(kvm_isa_ext_arr))
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return -ENOENT;
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kvm_ext = array_index_nospec(kvm_ext, ARRAY_SIZE(kvm_isa_ext_arr));
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switch (kvm_isa_ext_arr[kvm_ext]) {
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case RISCV_ISA_EXT_SMNPM:
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/*
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* Pointer masking effective in (H)S-mode is provided by the
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* Smnpm extension, so that extension is reported to the guest,
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* even though the CSR bits for configuring VS-mode pointer
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* masking on the host side are part of the Ssnpm extension.
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*/
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host_ext = RISCV_ISA_EXT_SSNPM;
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break;
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default:
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host_ext = kvm_isa_ext_arr[kvm_ext];
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break;
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}
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if (!__riscv_isa_extension_available(NULL, host_ext))
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return -ENOENT;
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if (base_ext)
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*base_ext = kvm_isa_ext_arr[kvm_ext];
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return 0;
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}
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bool kvm_riscv_isa_enable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_H:
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return false;
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case KVM_RISCV_ISA_EXT_SSCOFPMF:
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/* Sscofpmf depends on interrupt filtering defined in ssaia */
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return !kvm_riscv_isa_check_host(SSAIA);
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case KVM_RISCV_ISA_EXT_SVADU:
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/*
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* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
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* Guest OS can use Svadu only when host OS enable Svadu.
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*/
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return arch_has_hw_pte_young();
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case KVM_RISCV_ISA_EXT_V:
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return riscv_v_vstate_ctrl_user_allowed();
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default:
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break;
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}
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return true;
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}
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bool kvm_riscv_isa_disable_allowed(unsigned long ext)
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{
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switch (ext) {
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/* Extensions which don't have any mechanism to disable */
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case KVM_RISCV_ISA_EXT_A:
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case KVM_RISCV_ISA_EXT_C:
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case KVM_RISCV_ISA_EXT_I:
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case KVM_RISCV_ISA_EXT_M:
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/* There is not architectural config bit to disable sscofpmf completely */
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case KVM_RISCV_ISA_EXT_SSCOFPMF:
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case KVM_RISCV_ISA_EXT_SSNPM:
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case KVM_RISCV_ISA_EXT_SSTC:
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case KVM_RISCV_ISA_EXT_SVINVAL:
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case KVM_RISCV_ISA_EXT_SVNAPOT:
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case KVM_RISCV_ISA_EXT_SVVPTC:
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case KVM_RISCV_ISA_EXT_ZAAMO:
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case KVM_RISCV_ISA_EXT_ZABHA:
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case KVM_RISCV_ISA_EXT_ZACAS:
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case KVM_RISCV_ISA_EXT_ZALASR:
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case KVM_RISCV_ISA_EXT_ZALRSC:
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case KVM_RISCV_ISA_EXT_ZAWRS:
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case KVM_RISCV_ISA_EXT_ZBA:
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case KVM_RISCV_ISA_EXT_ZBB:
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case KVM_RISCV_ISA_EXT_ZBC:
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case KVM_RISCV_ISA_EXT_ZBKB:
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case KVM_RISCV_ISA_EXT_ZBKC:
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case KVM_RISCV_ISA_EXT_ZBKX:
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case KVM_RISCV_ISA_EXT_ZBS:
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case KVM_RISCV_ISA_EXT_ZCA:
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case KVM_RISCV_ISA_EXT_ZCB:
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case KVM_RISCV_ISA_EXT_ZCD:
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case KVM_RISCV_ISA_EXT_ZCF:
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case KVM_RISCV_ISA_EXT_ZCMOP:
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case KVM_RISCV_ISA_EXT_ZFA:
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case KVM_RISCV_ISA_EXT_ZFBFMIN:
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case KVM_RISCV_ISA_EXT_ZFH:
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case KVM_RISCV_ISA_EXT_ZFHMIN:
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case KVM_RISCV_ISA_EXT_ZICBOP:
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case KVM_RISCV_ISA_EXT_ZICCRSE:
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case KVM_RISCV_ISA_EXT_ZICNTR:
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case KVM_RISCV_ISA_EXT_ZICOND:
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case KVM_RISCV_ISA_EXT_ZICSR:
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case KVM_RISCV_ISA_EXT_ZIFENCEI:
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case KVM_RISCV_ISA_EXT_ZIHINTNTL:
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case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
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case KVM_RISCV_ISA_EXT_ZIHPM:
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case KVM_RISCV_ISA_EXT_ZIMOP:
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case KVM_RISCV_ISA_EXT_ZKND:
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case KVM_RISCV_ISA_EXT_ZKNE:
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case KVM_RISCV_ISA_EXT_ZKNH:
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case KVM_RISCV_ISA_EXT_ZKR:
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case KVM_RISCV_ISA_EXT_ZKSED:
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case KVM_RISCV_ISA_EXT_ZKSH:
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case KVM_RISCV_ISA_EXT_ZKT:
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case KVM_RISCV_ISA_EXT_ZTSO:
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case KVM_RISCV_ISA_EXT_ZVBB:
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case KVM_RISCV_ISA_EXT_ZVBC:
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case KVM_RISCV_ISA_EXT_ZVFBFMIN:
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case KVM_RISCV_ISA_EXT_ZVFBFWMA:
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case KVM_RISCV_ISA_EXT_ZVFH:
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case KVM_RISCV_ISA_EXT_ZVFHMIN:
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case KVM_RISCV_ISA_EXT_ZVKB:
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case KVM_RISCV_ISA_EXT_ZVKG:
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case KVM_RISCV_ISA_EXT_ZVKNED:
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case KVM_RISCV_ISA_EXT_ZVKNHA:
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case KVM_RISCV_ISA_EXT_ZVKNHB:
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case KVM_RISCV_ISA_EXT_ZVKSED:
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case KVM_RISCV_ISA_EXT_ZVKSH:
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case KVM_RISCV_ISA_EXT_ZVKT:
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return false;
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/* Extensions which can be disabled using Smstateen */
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case KVM_RISCV_ISA_EXT_SSAIA:
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return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN);
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case KVM_RISCV_ISA_EXT_SVADE:
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/*
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* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
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* Svade can't be disabled unless we support Svadu.
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*/
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return arch_has_hw_pte_young();
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default:
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break;
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}
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return true;
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}
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