Archit Taneja c1d97083cd drm/msm/dsi: Add byte_intf_clk ...

DSI6G v2.0+ blocks have a new clock input to them called
byte_intf_clk. It's rate is to be set as byte_clk / 2.

Within the clock controller (CC) subsystem, this clock is a
child/descendant of the byte_clk.

Set it up as an optional clock in the DSI host driver. Make sure
that we enable/set its rate only after we configure byte_clk.
This is required for the ancestor clocks in the CC to be
configured correctly.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

2018-02-20 10:41:21 -05:00

..

drm

drm/msm/dsi: Add byte_intf_clk

2018-02-20 10:41:21 -05:00

host1x

gpu: host1x: Use IOMMU groups

2017-12-21 14:52:36 +01:00

ipu-v3

gpu: ipu-v3: allow to build with COMPILE_TEST

2017-12-19 12:49:11 +01:00

vga

vfs: do bulk POLL* -> EPOLL* replacement

2018-02-11 14:34:03 -08:00

Makefile

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