Matt Roper 43571e15c0 drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets ...

All MG/DKL PHY register regions are evenly spaced offset-wise (0x168000,
0x169000, 0x16A000, 0x16B000) so the _MMIO_PORT() macro we use to access
their registers only needs the first two offsets.  We can drop the
_PORT3 and _PORT4 offsets which are never directly referenced.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-12-matthew.d.roper@intel.com

2022-01-11 14:03:26 -08:00

..

drm

drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets

2022-01-11 14:03:26 -08:00

host1x

gpu: host1x: Plug potential memory leak

2021-09-16 18:06:52 +02:00

ipu-v3

media: i.MX6: Support 16-bit BT.1120 video input

2021-10-19 08:08:38 +01:00

trace

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vga

vgaarb: don't pass a cookie to vga_client_register

2021-07-21 10:29:10 +02:00

Makefile

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