Daniele Ceraolo Spurio 3d2b5d4e28 drm/xe: add GSCCS irq support ...

The GSCCS has its own enable and mask registers. The interrupt identity
for the GSCCS shows OTHER_CLASS instance 6.

Bspec: 54029, 54030
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230817201831.1583172-4-daniele.ceraolospurio@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

2023-12-21 11:40:20 -05:00

..

drm

drm/xe: add GSCCS irq support

2023-12-21 11:40:20 -05:00

host1x

gpu: host1x: Correct allocated size for contexts

2023-10-11 22:52:44 +02:00

ipu-v3

Merge tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drm

2023-08-30 13:34:34 -07:00

trace

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vga

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Makefile

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