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20b522e812
The CSI-2 receiver in the i.MX8ULP is almost identical to the version present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk clock as the input clock for its APB interface of Control and Status register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and increase maxItems of Clocks (clock-names) to 4 from 3. And keep the same restriction for existing compatible. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> Link: https://patch.msgid.link/20251205-csi2_imx8ulp-v10-1-190cdadb20a3@nxp.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>