mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-27 20:42:27 -04:00
b9d8a295ed
Pull misc x86 updates from Borislav Petkov: - The first part of a restructuring of AMD's representation of a northbridge which is legacy now, and the creation of the new AMD node concept which represents the Zen architecture of having a collection of I/O devices within an SoC. Those nodes comprise the so-called data fabric on Zen. This has at least one practical advantage of not having to add a PCI ID each time a new data fabric PCI device releases. Eventually, the lot more uniform provider of data fabric functionality amd_node.c will be used by all the drivers which need it - Smaller cleanups * tag 'x86_misc_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/amd_node: Use defines for SMN register offsets x86/amd_node: Remove dependency on AMD_NB x86/amd_node: Update __amd_smn_rw() error paths x86/amd_nb: Move SMN access code to a new amd_node driver x86/amd_nb, hwmon: (k10temp): Simplify amd_pci_dev_to_node_id() x86/amd_nb: Simplify function 3 search x86/amd_nb: Use topology info to get AMD node count x86/amd_nb: Simplify root device search x86/amd_nb: Simplify function 4 search x86: Start moving AMD node functionality out of AMD_NB x86/amd_nb: Clean up early_is_amd_nb() x86/amd_nb: Restrict init function to AMD-based systems x86/mtrr: Rename mtrr_overwrite_state() to guest_force_mtrr_state()
79 lines
1.6 KiB
C
79 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_AMD_NB_H
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#define _ASM_X86_AMD_NB_H
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <asm/amd_node.h>
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struct amd_nb_bus_dev_range {
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u8 bus;
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u8 dev_base;
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u8 dev_limit;
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};
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extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
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extern bool early_is_amd_nb(u32 value);
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extern struct resource *amd_get_mmconfig_range(struct resource *res);
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extern void amd_flush_garts(void);
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extern int amd_numa_init(void);
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extern int amd_get_subcaches(int);
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extern int amd_set_subcaches(int, unsigned long);
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struct amd_l3_cache {
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unsigned indices;
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u8 subcaches[4];
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};
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struct amd_northbridge {
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struct pci_dev *root;
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struct pci_dev *misc;
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struct pci_dev *link;
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struct amd_l3_cache l3_cache;
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};
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struct amd_northbridge_info {
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u16 num;
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u64 flags;
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struct amd_northbridge *nb;
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};
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#define AMD_NB_GART BIT(0)
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#define AMD_NB_L3_INDEX_DISABLE BIT(1)
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#define AMD_NB_L3_PARTITIONING BIT(2)
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#ifdef CONFIG_AMD_NB
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u16 amd_nb_num(void);
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bool amd_nb_has_feature(unsigned int feature);
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struct amd_northbridge *node_to_amd_nb(int node);
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static inline bool amd_gart_present(void)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return false;
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/* GART present only on Fam15h, up to model 0fh */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
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(boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
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return true;
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return false;
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}
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#else
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#define amd_nb_num(x) 0
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#define amd_nb_has_feature(x) false
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static inline struct amd_northbridge *node_to_amd_nb(int node)
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{
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return NULL;
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}
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#define amd_gart_present(x) false
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#endif
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#endif /* _ASM_X86_AMD_NB_H */
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