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6acf3d3ed6
The number of registers used to express the XeCore mask has some "special cases" that don't always get inherited by later IP versions so it's cleaner and simpler to record the numbers in the IP descriptor rather than adding extra conditions to the standalone get_num_dss_regs() function. Note that a minor change here is that we now always treat the number of registers as 0 for the media GT. Technically a copy of these fuse registers does exist in the media GT as well (at the usual 0x380000+$offset location), but the value of those is always supposed to read back as 0 because media GTs never have any XeCores or EUs. v2: - Add a kunit assertion to catch descriptors that forget to initialize either count. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20260205214139.48515-3-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include <drm/drm_drv.h>
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#include <drm/drm_kunit_helpers.h>
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#include <kunit/test.h>
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#include "tests/xe_test.h"
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#include "xe_device.h"
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#include "xe_pci_test.h"
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#include "xe_pci_types.h"
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static void check_graphics_ip(struct kunit *test)
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{
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const struct xe_ip *param = test->param_value;
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const struct xe_graphics_desc *graphics = param->desc;
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u64 mask = graphics->hw_engine_mask;
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u8 fuse_regs = graphics->num_geometry_xecore_fuse_regs +
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graphics->num_compute_xecore_fuse_regs;
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/* RCS, CCS, and BCS engines are allowed on the graphics IP */
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mask &= ~(XE_HW_ENGINE_RCS_MASK |
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XE_HW_ENGINE_CCS_MASK |
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XE_HW_ENGINE_BCS_MASK);
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/* Any remaining engines are an error */
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KUNIT_ASSERT_EQ(test, mask, 0);
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/*
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* All graphics IP should have at least one geometry and/or compute
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* XeCore fuse register.
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*/
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KUNIT_ASSERT_GE(test, fuse_regs, 1);
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}
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static void check_media_ip(struct kunit *test)
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{
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const struct xe_ip *param = test->param_value;
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const struct xe_media_desc *media = param->desc;
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u64 mask = media->hw_engine_mask;
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/* VCS, VECS and GSCCS engines are allowed on the media IP */
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mask &= ~(XE_HW_ENGINE_VCS_MASK |
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XE_HW_ENGINE_VECS_MASK |
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XE_HW_ENGINE_GSCCS_MASK);
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/* Any remaining engines are an error */
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KUNIT_ASSERT_EQ(test, mask, 0);
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}
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static void check_platform_desc(struct kunit *test)
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{
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const struct pci_device_id *pci = test->param_value;
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const struct xe_device_desc *desc =
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(const struct xe_device_desc *)pci->driver_data;
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KUNIT_EXPECT_GT(test, desc->dma_mask_size, 0);
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KUNIT_EXPECT_GT(test, (unsigned int)desc->max_gt_per_tile, 0);
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KUNIT_EXPECT_LE(test, (unsigned int)desc->max_gt_per_tile, XE_MAX_GT_PER_TILE);
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KUNIT_EXPECT_GT(test, desc->va_bits, 0);
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KUNIT_EXPECT_LE(test, desc->va_bits, 64);
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KUNIT_EXPECT_GT(test, desc->vm_max_level, 0);
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}
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static struct kunit_case xe_pci_tests[] = {
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KUNIT_CASE_PARAM(check_graphics_ip, xe_pci_graphics_ip_gen_param),
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KUNIT_CASE_PARAM(check_media_ip, xe_pci_media_ip_gen_param),
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KUNIT_CASE_PARAM(check_platform_desc, xe_pci_id_gen_param),
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{}
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};
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static struct kunit_suite xe_pci_test_suite = {
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.name = "xe_pci",
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.test_cases = xe_pci_tests,
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};
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kunit_test_suite(xe_pci_test_suite);
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