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f6c39feed0
Add L3SQCREG5 as part of HW recommended settings. The recommended value in Bspec is 00e0007f. For Xe2-LPG, bits 23:21 don't exist anymore, but it's confirmed with HW engineers that setting them doesn't do anything. They still exist on the media GT, Xe2-LPM, but they are already they are already set as per HW default value. So for Xe2 platform, the only bits that need to be set are 9:0 since HW's default is 0x1ff and the recommended value is 0x7f. Unlike most registers, which have the same relative offset on both the primary and media GT, this register has a different base offset on the media GT. On MTL the register only exists for the primary (graphics) GT, so there's no need to program it on the media gt. Also, it's part of the RCS engine's context, so it needs to be added as a LRC workaround. Bspec: 72161 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20231024220739.224251-2-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_tuning.h"
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#include <kunit/visibility.h>
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#include "regs/xe_gt_regs.h"
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#include "xe_gt_types.h"
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#include "xe_platform_types.h"
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#include "xe_rtp.h"
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#undef XE_REG_MCR
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#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
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static const struct xe_rtp_entry_sr gt_tunings[] = {
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{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
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XE_RTP_RULES(PLATFORM(DG2)),
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XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
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},
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{ XE_RTP_NAME("Tuning: 32B Access Enable"),
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XE_RTP_RULES(PLATFORM(DG2)),
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XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
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},
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/* Xe2 */
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{ XE_RTP_NAME("Tuning: L3 cache"),
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XE_RTP_RULES(GRAPHICS_VERSION(2004)),
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XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{ XE_RTP_NAME("Tuning: L3 cache - media"),
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XE_RTP_RULES(MEDIA_VERSION(2000)),
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XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{}
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};
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static const struct xe_rtp_entry_sr engine_tunings[] = {
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{ XE_RTP_NAME("Tuning: Set Indirect State Override"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1271),
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ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))
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},
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{}
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};
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static const struct xe_rtp_entry_sr lrc_tunings[] = {
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{ XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
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/* read verification is ignored due to 1608008084. */
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XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
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FF_MODE2_GS_TIMER_MASK,
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FF_MODE2_GS_TIMER_224))
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},
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/* DG2 */
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{ XE_RTP_NAME("Tuning: L3 cache"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{ XE_RTP_NAME("Tuning: TDS gang timer"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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/* read verification is ignored as in i915 - need to check enabling */
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XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
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FF_MODE2_TDS_TIMER_MASK,
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FF_MODE2_TDS_TIMER_128))
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},
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{ XE_RTP_NAME("Tuning: TBIMR fast clip"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
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},
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/* Xe_LPG */
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{ XE_RTP_NAME("Tuning: L3 cache"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{}
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};
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void xe_tuning_process_gt(struct xe_gt *gt)
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{
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
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xe_rtp_process_to_sr(&ctx, gt_tunings, >->reg_sr);
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}
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EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
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void xe_tuning_process_engine(struct xe_hw_engine *hwe)
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{
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
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xe_rtp_process_to_sr(&ctx, engine_tunings, &hwe->reg_sr);
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}
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EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
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/**
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* xe_tuning_process_lrc - process lrc tunings
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* @hwe: engine instance to process tunings for
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*
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* Process LRC table for this platform, saving in @hwe all the tunings that need
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* to be applied on context restore. These are tunings touching registers that
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* are part of the HW context image.
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*/
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void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
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{
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
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xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc);
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}
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