Ville Syrjälä 2e523e98bb drm/i915: Implement chv display PHY lane stagger setup ...

Set up the chv display PHY lane stagger registers according to
"Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by:  Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2015-05-08 15:55:22 +02:00

..

drm

drm/i915: Implement chv display PHY lane stagger setup

2015-05-08 15:55:22 +02:00

host1x

gpu: host1x: Export host1x_syncpt_read()

2015-04-02 18:46:20 +02:00

ipu-v3

Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next

2015-04-13 17:28:57 +10:00

vga

Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-10-13 16:23:15 +02:00

Makefile

gpu: host1x: Provide a proper struct bus_type

2015-01-27 10:09:14 +01:00