Martin Leung d5349775c1 drm/amd/display: update soc bb for nv14 ...

[why]
nv14 previously inherited soc bb from generic dcn 2, did not match
watermark values according to memory team

[how]
add nv14 specific soc bb: copy nv2 generic that it was
using from before, but changed num channels to 8

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-03-09 15:06:55 -04:00

..

amdgpu_dm

drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2)

2020-03-05 09:42:08 -05:00

dc

drm/amd/display: update soc bb for nv14

2020-03-09 15:06:55 -04:00

dmub

drm/amd/display: Check hw_init state when determining if DMCUB is initialized

2020-01-22 16:55:28 -05:00

include

drm/amd/display: add Pollock IDs, fix Pollock & Dali clk mgr construct

2020-01-14 10:18:10 -05:00

modules

drm/amd/display: fix backwards byte order in rx_caps.

2020-02-14 12:58:58 -05:00

Kconfig

amdgpu: Enable initial DCN support on POWER

2019-12-18 16:09:05 -05:00

Makefile

drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards

2019-11-13 15:29:42 -05:00

TODO

drm/amd/display: Convert remaining loggers off dc_logger

2018-07-13 14:48:42 -05:00