Geert Uytterhoeven 625af11fb9 arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts ...

Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers.  Drop the masks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

2026-03-30 21:27:28 -05:00

..

keembay-evm.dts

arm64: dts: keembay: Add device tree for Keem Bay EVM board

2020-07-17 16:32:20 +02:00

keembay-soc.dtsi

arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage

2024-04-29 10:27:52 +02:00

Makefile

arm64: dts: socfpga: agilex: add emmc support

2026-01-30 09:44:46 -06:00

socfpga_agilex3_socdk.dts

arm64: dts: socfpga: add Agilex3 board

2025-11-14 07:00:22 -06:00

socfpga_agilex5_socdk_013b.dts

arm64: dts: socfpga: agilex5: update qspi partitions for 013b board

2025-11-17 05:37:59 -06:00

socfpga_agilex5_socdk_modular.dts

arm64: dts: socfpga: agilex5: add support for modular board

2026-01-30 09:27:12 -06:00

socfpga_agilex5_socdk_nand.dts

arm64: dts: agilex5: Add GMAC0 node for NAND daughter card

2025-10-14 22:13:09 -05:00

socfpga_agilex5_socdk.dts

arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

2025-10-14 22:07:56 -05:00

socfpga_agilex5.dtsi

arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts

2026-03-30 21:27:28 -05:00

socfpga_agilex_n6000.dts

arm64: dts: socfpga: agilex: add unit address to soc node

2024-01-03 18:10:40 -06:00

socfpga_agilex_socdk_emmc.dts

arm64: dts: socfpga: agilex: add emmc support

2026-01-30 09:44:46 -06:00

socfpga_agilex_socdk_nand.dts

arm64: dts: socfpga: agilex: fix dtbs_check warning for NAND

2025-10-30 16:51:59 -05:00

socfpga_agilex_socdk.dts

arm64: dts: altera: Use lowercase hex

2026-01-30 09:27:12 -06:00

socfpga_agilex.dtsi

arm64: dts: socfpga: agilex: fix dtbs_check warning for clock manager

2025-10-30 16:51:59 -05:00

socfpga_n5x_socdk.dts

arm64: dts: altera: Use lowercase hex

2026-01-30 09:27:12 -06:00