Thierry Reding 28fe207600 drm/tegra: sor: Registers are 32-bit ...

Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>

2015-04-02 18:46:16 +02:00

..

drm

drm/tegra: sor: Registers are 32-bit

2015-04-02 18:46:16 +02:00

host1x

gpu: host1x: Provide a proper struct bus_type

2015-01-27 10:09:14 +01:00

ipu-v3

Merge tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux into drm-next

2015-02-11 15:35:26 +10:00

vga

Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-10-13 16:23:15 +02:00

Makefile

gpu: host1x: Provide a proper struct bus_type

2015-01-27 10:09:14 +01:00