mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-06-02 04:02:30 -04:00
0774c43c00
Add documentation for the serial communication interface (RSCI) found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets. It has 6 interrupts compared to 4 on RZ/T2H. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20251129164325.209213-2-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>