Madhav Chauhan 27efd2566c drm/i915/icl: Define register for DSI PLL ...

This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.

v2: Review comments from Jani N
    - Fix spaces while defining ICL_ESC_CLK_DIV_MASK
    - Define shift and mask for bitfields.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530795727-28644-2-git-send-email-madhav.chauhan@intel.com

2018-07-05 16:27:56 +03:00

..

drm

drm/i915/icl: Define register for DSI PLL

2018-07-05 16:27:56 +03:00

host1x

gpu: host1x: Use IOMMU groups

2017-12-21 14:52:36 +01:00

ipu-v3

gpu: ipu-v3: prg: avoid possible array underflow

2018-03-15 17:52:08 +01:00

vga

vga_switcheroo: Let HDA autosuspend on mux change

2018-03-13 22:58:49 +01:00

Makefile

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