Hyungwon Hwang 26269af95a drm/exynos: dsi: rename pll_clk to sclk_clk ...

This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

2015-06-22 20:05:00 +09:00

..

drm

drm/exynos: dsi: rename pll_clk to sclk_clk

2015-06-22 20:05:00 +09:00

host1x

gpu: host1x: Export host1x_syncpt_read()

2015-04-02 18:46:20 +02:00

ipu-v3

Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next

2015-04-13 17:28:57 +10:00

vga

Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-10-13 16:23:15 +02:00

Makefile

gpu: host1x: Provide a proper struct bus_type

2015-01-27 10:09:14 +01:00