Likun Gao 25fc05648f drm/amdgpu/mes: correct register offset for sienna_cichlid ...

Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-07-01 01:59:09 -04:00

..

drm

drm/amdgpu/mes: correct register offset for sienna_cichlid

2020-07-01 01:59:09 -04:00

host1x

Merge tag 'drm/tegra/for-5.6-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next

2020-02-07 12:22:30 +10:00

ipu-v3

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trace

gpu/trace: add a gpu total memory usage tracepoint

2020-03-03 17:52:41 -05:00

vga

vga: Fix Kconfig indentation

2019-11-20 17:40:32 +01:00

Makefile

gpu/trace: add a gpu total memory usage tracepoint

2020-03-03 17:52:41 -05:00