Rob Herring 7d9ef7f37d dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes ...

Matching on the 'cpus' node was a bad choice because the schema is
incorrectly applied to non-RiscV cpus nodes. As we now have a common cpus
schema which checks the general structure, it is also redundant to do so
in the Risc-V CPU schema.

The downside is one could conceivably mix different architecture's cpu
nodes or have typos in the compatible string. The latter problem pretty
much exists for every schema.

Acked-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Rob Herring <robh@kernel.org>

2019-07-20 20:28:52 -06:00

..

cpus.txt

dt-bindings: RISC-V CPU Bindings

2017-09-25 15:50:57 -07:00

cpus.yaml

dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes

2019-07-20 20:28:52 -06:00

sifive-l2-cache.txt

RISC-V: Add DT documentation for SiFive L2 Cache Controller

2019-05-16 20:42:13 -07:00

sifive.yaml

dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540

2019-06-17 02:03:52 -07:00