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Merge series from David Lechner <dlechner@baylibre.com>: In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK using the SPI offload feature of the AXI SPI Engine, we need to shave off some time that is spent executing unnecessary instructions. There are a few one-time setup instructions that can be moved so that they execute only once when the SPI offload trigger is enabled rather than repeating each time the offload is triggered. Additionally, a recent change to the IP block allows dropping the SYNC instruction completely. With these changes, we are left with only the 3 instructions that are needed to to assert CS, transfer the data, and deassert CS. This makes 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the available time period.