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1cd5bb6e9e
Replace the RISCV_ISA_V dependency of the RISC-V crypto code with RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS, which implies RISCV_ISA_V as well as vector unaligned accesses being efficient. This is necessary because this code assumes that vector unaligned accesses are supported and are efficient. (It does so to avoid having to use lots of extra vsetvli instructions to switch the element width back and forth between 8 and either 32 or 64.) This was omitted from the code originally just because the RISC-V kernel support for detecting this feature didn't exist yet. Support has now been added, but it's fragmented into per-CPU runtime detection, a command-line parameter, and a kconfig option. The kconfig option is the only reasonable way to do it, though, so let's just rely on that. Fixes:eb24af5d7a("crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}") Fixes:bb54668837("crypto: riscv - add vector crypto accelerated ChaCha20") Fixes:600a3853df("crypto: riscv - add vector crypto accelerated GHASH") Fixes:8c8e40470f("crypto: riscv - add vector crypto accelerated SHA-{256,224}") Fixes:b3415925a0("crypto: riscv - add vector crypto accelerated SHA-{512,384}") Fixes:563a5255af("crypto: riscv - add vector crypto accelerated SM3") Fixes:b8d06352bb("crypto: riscv - add vector crypto accelerated SM4") Cc: stable@vger.kernel.org Reported-by: Vivian Wang <wangruikang@iscas.ac.cn> Closes: https://lore.kernel.org/r/b3cfcdac-0337-4db0-a611-258f2868855f@iscas.ac.cn/ Reviewed-by: Jerry Shih <jerry.shih@sifive.com> Link: https://lore.kernel.org/r/20251206213750.81474-1-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
65 lines
1.9 KiB
Plaintext
65 lines
1.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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menu "Accelerated Cryptographic Algorithms for CPU (riscv)"
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config CRYPTO_AES_RISCV64
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tristate "Ciphers: AES, modes: ECB, CBC, CTS, CTR, XTS"
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depends on 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
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RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS
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select CRYPTO_ALGAPI
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select CRYPTO_LIB_AES
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select CRYPTO_SKCIPHER
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help
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Block cipher: AES cipher algorithms
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Length-preserving ciphers: AES with ECB, CBC, CTS, CTR, XTS
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Architecture: riscv64 using:
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- Zvkned vector crypto extension
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- Zvbb vector extension (XTS)
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- Zvkb vector crypto extension (CTR)
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- Zvkg vector crypto extension (XTS)
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config CRYPTO_GHASH_RISCV64
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tristate "Hash functions: GHASH"
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depends on 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
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RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS
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select CRYPTO_GCM
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help
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GCM GHASH function (NIST SP 800-38D)
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Architecture: riscv64 using:
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- Zvkg vector crypto extension
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config CRYPTO_SM3_RISCV64
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tristate "Hash functions: SM3 (ShangMi 3)"
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depends on 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
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RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS
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select CRYPTO_HASH
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select CRYPTO_LIB_SM3
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help
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SM3 (ShangMi 3) secure hash function (OSCCA GM/T 0004-2012)
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Architecture: riscv64 using:
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- Zvksh vector crypto extension
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- Zvkb vector crypto extension
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config CRYPTO_SM4_RISCV64
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tristate "Ciphers: SM4 (ShangMi 4)"
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depends on 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
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RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS
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select CRYPTO_ALGAPI
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select CRYPTO_SM4
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help
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SM4 block cipher algorithm (OSCCA GB/T 32907-2016,
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ISO/IEC 18033-3:2010/Amd 1:2021)
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SM4 (GBT.32907-2016) is a cryptographic standard issued by the
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Organization of State Commercial Administration of China (OSCCA)
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as an authorized cryptographic algorithm for use within China.
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Architecture: riscv64 using:
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- Zvksed vector crypto extension
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- Zvkb vector crypto extension
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endmenu
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