Ken Chalmers 18e4aa33bd
drm/amd/display: eliminate long wait between register polls on Maximus ...
[Why]
Now that we "scale" time delays correctly on Maximus (as of diags svn
r170115), the forced "35 ms" wait time now becomes 35 ms * 500 = 17.5
seconds, which is far too long. Even having to repeat polling a
register once causes excessive delays on Maximus.
[How]
Just use the regular wait time passed to the generic_reg_wait()
function. This is sufficient for Maximus now, and it also means that
there's one less "Maximus-only" code path in DAL.
Also disable the "REG_WAIT taking a while:" message on Maximus, since
things do take a while longer there and 1-2ms delays are not uncommon
(and nothing to worry about).
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com >
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com >
Acked-by: Leo Li <sunpeng.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-08-27 15:20:24 -05:00
2018-08-25 18:13:10 -07:00
2018-08-08 11:05:47 +02:00
2018-08-24 13:20:33 -07:00
2018-08-18 11:04:51 -07:00
2018-08-18 11:44:53 -07:00
2018-08-26 11:48:42 -07:00
2018-08-13 15:59:39 +02:00
2018-08-23 13:52:46 -07:00
2018-08-02 15:22:39 -06:00
2018-08-20 16:30:27 -07:00
2018-08-23 13:52:46 -07:00
2018-08-19 09:56:38 -07:00
2018-08-23 13:52:46 -07:00
2018-08-22 07:42:36 -07:00
2018-08-23 19:20:12 -07:00
2018-08-25 18:43:59 -07:00
2018-08-18 11:04:51 -07:00
2018-08-26 11:48:42 -07:00
2018-08-17 15:13:34 +02:00
2018-08-17 16:20:27 -07:00
2018-08-23 15:44:58 -07:00
2018-08-08 15:44:47 +10:00
2018-08-20 15:38:44 -07:00
2018-08-27 15:20:24 -05:00
2018-08-20 15:59:01 -07:00
2018-08-02 10:20:59 +02:00
2018-08-23 13:52:46 -07:00
2018-07-30 20:54:51 -07:00
2018-08-23 18:48:43 -07:00
2018-08-24 17:26:43 +02:00
2018-08-22 07:40:33 -07:00
2018-08-23 18:48:43 -07:00
2018-08-23 15:34:48 -07:00
2018-08-23 13:44:43 -07:00
2018-08-25 14:12:36 -07:00
2018-08-26 09:55:28 -07:00
2018-08-16 12:26:24 -07:00
2018-08-06 23:03:12 +02:00
2018-08-24 14:42:42 +02:00
2018-08-15 09:53:07 +05:30
2018-08-25 18:13:10 -07:00
2018-08-26 11:48:42 -07:00
2018-08-23 13:52:46 -07:00
2018-07-30 23:17:53 -04:00
2018-08-21 17:40:46 -07:00
2018-08-26 11:48:42 -07:00
2018-08-09 14:47:05 +01:00
2018-08-23 15:58:04 -07:00
2018-08-02 10:23:02 +02:00
2018-08-23 13:44:43 -07:00
2018-08-25 18:43:59 -07:00
2018-08-16 14:21:29 -06:00
2018-08-15 15:04:25 -07:00
2018-08-18 11:04:51 -07:00
2018-08-22 12:34:08 -07:00
2018-08-18 12:30:42 -07:00
2018-08-18 11:04:51 -07:00
2018-07-30 10:04:58 +02:00
2018-08-20 15:38:44 -07:00
2018-08-22 14:14:15 -07:00
2018-08-23 18:48:43 -07:00
2018-08-18 11:04:51 -07:00
2018-08-20 11:36:07 +02:00
2018-08-22 10:52:51 -07:00
2018-08-20 15:38:44 -07:00
2018-08-16 17:39:55 -07:00
2018-08-25 14:12:36 -07:00
2018-07-30 23:40:23 -07:00
2018-08-20 16:30:27 -07:00
2018-08-25 18:13:10 -07:00
2018-08-26 11:48:42 -07:00
2018-08-02 13:54:06 +02:00
2018-08-23 14:02:22 -07:00
2018-08-18 16:45:27 -07:00
2018-08-09 18:47:47 +03:00
2018-08-23 13:52:46 -07:00
2018-08-26 11:48:42 -07:00
2018-08-23 13:52:46 -07:00
2018-08-24 13:03:51 -07:00
2018-08-24 09:34:23 -07:00
2018-08-19 09:30:44 -07:00
2018-08-23 13:52:46 -07:00
2018-08-17 11:32:50 -07:00
2018-08-24 08:45:19 -07:00
2018-08-23 15:44:58 -07:00
2018-08-24 08:45:19 -07:00
2018-08-21 18:06:27 -07:00
2018-08-22 17:31:34 -07:00
2018-08-23 14:52:23 -07:00
2018-08-18 11:04:51 -07:00
18e4aa33bd