Rohit Khaire 18703923a6 drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid ...

RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2021-06-04 16:02:44 -04:00

..

drm

drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

2021-06-04 16:02:44 -04:00

host1x

gpu: host1x: Add early init and late exit callbacks

2021-03-31 17:42:14 +02:00

ipu-v3

gpu: ipu-v3: Add Rec.709 limited range support to DP

2021-05-10 17:20:29 +02:00

trace

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vga

vgaarb: Use ACPI HID name to find integrated GPU

2021-05-20 14:55:56 -04:00

Makefile

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