mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-29 20:58:57 -04:00
08326b92c7
Fix a runtime assertion in setup_xor_mapping(). Fortify complains that it
is potentially overflowing the xormaps array per __counted_by(nr_maps).
Quiet the false positive by initializing @nr_maps earlier.
memcpy: detected buffer overflow: 32 byte write of buffer size 0
WARNING: lib/string_helpers.c:1036 at __fortify_report+0x4d/0xa0, CPU#8: modprobe/2728
Call Trace:
__fortify_panic+0xd/0xf
setup_xor_mapping+0x6c/0xa0 [cxl_translate]
[ dj: Fixed up @nr_entries to @nr_maps in commit log. ]
Fixes: 06377c54a1 ("cxl/test: Add cxl_translate module for address translation testing")
Signed-off-by: Dan Williams <djbw@kernel.org>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20260519221204.1517773-3-djbw@kernel.org
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
452 lines
13 KiB
C
452 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright(c) 2025 Intel Corporation. All rights reserved.
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/* Preface all log entries with "cxl_translate" */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/moduleparam.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <cxlmem.h>
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#include <cxl.h>
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/* Maximum number of test vectors and entry length */
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#define MAX_TABLE_ENTRIES 128
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#define MAX_ENTRY_LEN 128
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/* Expected number of parameters in each test vector */
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#define EXPECTED_PARAMS 7
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/* Module parameters for test vectors */
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static char *table[MAX_TABLE_ENTRIES];
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static int table_num;
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/* Interleave Arithmetic */
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#define MODULO_MATH 0
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#define XOR_MATH 1
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/*
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* XOR mapping configuration
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* The test data sets all use the same set of xormaps. When additional
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* data sets arrive for validation, this static setup will need to
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* be changed to accept xormaps as additional parameters.
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*/
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struct cxl_cxims_data *cximsd;
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static u64 xormaps[] = {
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0x2020900,
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0x4041200,
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0x1010400,
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0x800,
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};
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static int nr_maps = ARRAY_SIZE(xormaps);
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#define HBIW_TO_NR_MAPS_SIZE (CXL_DECODER_MAX_INTERLEAVE + 1)
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static const int hbiw_to_nr_maps[HBIW_TO_NR_MAPS_SIZE] = {
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[1] = 0, [2] = 1, [3] = 0, [4] = 2, [6] = 1, [8] = 3, [12] = 2, [16] = 4
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};
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/**
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* to_hpa - calculate an HPA offset from a DPA offset and position
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*
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* dpa_offset: device physical address offset
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* pos: devices position in interleave
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* r_eiw: region encoded interleave ways
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* r_eig: region encoded interleave granularity
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* hb_ways: host bridge interleave ways
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* math: interleave arithmetic (MODULO_MATH or XOR_MATH)
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*
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* Returns: host physical address offset
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*/
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static u64 to_hpa(u64 dpa_offset, int pos, u8 r_eiw, u16 r_eig, u8 hb_ways,
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u8 math)
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{
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u64 hpa_offset;
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/* Calculate base HPA offset from DPA and position */
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hpa_offset = cxl_calculate_hpa_offset(dpa_offset, pos, r_eiw, r_eig);
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if (hpa_offset == ULLONG_MAX)
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return ULLONG_MAX;
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if (math == XOR_MATH) {
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cximsd->nr_maps = hbiw_to_nr_maps[hb_ways];
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if (cximsd->nr_maps)
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return cxl_do_xormap_calc(cximsd, hpa_offset, hb_ways);
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}
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return hpa_offset;
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}
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/**
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* to_dpa - translate an HPA offset to DPA offset
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*
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* hpa_offset: host physical address offset
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* r_eiw: region encoded interleave ways
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* r_eig: region encoded interleave granularity
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* hb_ways: host bridge interleave ways
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* math: interleave arithmetic (MODULO_MATH or XOR_MATH)
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*
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* Returns: device physical address offset
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*/
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static u64 to_dpa(u64 hpa_offset, u8 r_eiw, u16 r_eig, u8 hb_ways, u8 math)
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{
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u64 offset = hpa_offset;
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if (math == XOR_MATH) {
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cximsd->nr_maps = hbiw_to_nr_maps[hb_ways];
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if (cximsd->nr_maps)
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offset =
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cxl_do_xormap_calc(cximsd, hpa_offset, hb_ways);
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}
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return cxl_calculate_dpa_offset(offset, r_eiw, r_eig);
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}
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/**
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* to_pos - extract an interleave position from an HPA offset
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*
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* hpa_offset: host physical address offset
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* r_eiw: region encoded interleave ways
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* r_eig: region encoded interleave granularity
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* hb_ways: host bridge interleave ways
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* math: interleave arithmetic (MODULO_MATH or XOR_MATH)
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*
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* Returns: devices position in region interleave
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*/
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static u64 to_pos(u64 hpa_offset, u8 r_eiw, u16 r_eig, u8 hb_ways, u8 math)
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{
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u64 offset = hpa_offset;
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/* Reverse XOR mapping if specified */
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if (math == XOR_MATH)
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offset = cxl_do_xormap_calc(cximsd, hpa_offset, hb_ways);
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return cxl_calculate_position(offset, r_eiw, r_eig);
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}
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/**
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* run_translation_test - execute forward and reverse translations
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*
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* @dpa: device physical address
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* @pos: expected position in region interleave
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* @r_eiw: region encoded interleave ways
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* @r_eig: region encoded interleave granularity
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* @hb_ways: host bridge interleave ways
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* @math: interleave arithmetic (MODULO_MATH or XOR_MATH)
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* @expect_spa: expected system physical address
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*
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* Returns: 0 on success, -1 on failure
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*/
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static int run_translation_test(u64 dpa, int pos, u8 r_eiw, u16 r_eig,
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u8 hb_ways, int math, u64 expect_hpa)
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{
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u64 translated_spa, reverse_dpa;
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int reverse_pos;
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/* Test Device to Host translation: DPA + POS -> SPA */
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translated_spa = to_hpa(dpa, pos, r_eiw, r_eig, hb_ways, math);
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if (translated_spa != expect_hpa) {
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pr_err("Device to host failed: expected HPA %llu, got %llu\n",
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expect_hpa, translated_spa);
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return -1;
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}
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/* Test Host to Device DPA translation: SPA -> DPA */
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reverse_dpa = to_dpa(translated_spa, r_eiw, r_eig, hb_ways, math);
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if (reverse_dpa != dpa) {
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pr_err("Host to Device DPA failed: expected %llu, got %llu\n",
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dpa, reverse_dpa);
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return -1;
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}
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/* Test Host to Device Position translation: SPA -> POS */
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reverse_pos = to_pos(translated_spa, r_eiw, r_eig, hb_ways, math);
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if (reverse_pos != pos) {
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pr_err("Position lookup failed: expected %d, got %d\n", pos,
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reverse_pos);
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return -1;
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}
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return 0;
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}
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/**
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* parse_test_vector - parse a single test vector string
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*
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* entry: test vector string to parse
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* dpa: device physical address
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* pos: expected position in region interleave
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* r_eiw: region encoded interleave ways
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* r_eig: region encoded interleave granularity
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* hb_ways: host bridge interleave ways
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* math: interleave arithmetic (MODULO_MATH or XOR_MATH)
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* expect_spa: expected system physical address
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*
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* Returns: 0 on success, negative error code on failure
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*/
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static int parse_test_vector(const char *entry, u64 *dpa, int *pos, u8 *r_eiw,
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u16 *r_eig, u8 *hb_ways, int *math,
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u64 *expect_hpa)
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{
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unsigned int tmp_r_eiw, tmp_r_eig, tmp_hb_ways;
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int parsed;
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parsed = sscanf(entry, "%llu %d %u %u %u %d %llu", dpa, pos, &tmp_r_eiw,
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&tmp_r_eig, &tmp_hb_ways, math, expect_hpa);
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if (parsed != EXPECTED_PARAMS) {
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pr_err("Parse error: expected %d parameters, got %d in '%s'\n",
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EXPECTED_PARAMS, parsed, entry);
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return -EINVAL;
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}
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if (tmp_r_eiw > U8_MAX || tmp_r_eig > U16_MAX || tmp_hb_ways > U8_MAX) {
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pr_err("Parameter overflow in entry: '%s'\n", entry);
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return -ERANGE;
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}
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if (*math != MODULO_MATH && *math != XOR_MATH) {
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pr_err("Invalid math type %d in entry: '%s'\n", *math, entry);
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return -EINVAL;
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}
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*r_eiw = tmp_r_eiw;
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*r_eig = tmp_r_eig;
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*hb_ways = tmp_hb_ways;
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return 0;
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}
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/*
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* setup_xor_mapping - Initialize XOR mapping data structure
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*
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* The test data sets all use the same HBIG so we can use one set
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* of xormaps, and set the number to apply based on HBIW before
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* calling cxl_do_xormap_calc().
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*
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* When additional data sets arrive for validation with different
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* HBIG's this static setup will need to be updated.
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*
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* Returns: 0 on success, negative error code on failure
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*/
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static int setup_xor_mapping(void)
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{
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if (nr_maps <= 0)
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return -EINVAL;
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cximsd = kzalloc(struct_size(cximsd, xormaps, nr_maps), GFP_KERNEL);
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if (!cximsd)
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return -ENOMEM;
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cximsd->nr_maps = nr_maps;
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memcpy(cximsd->xormaps, xormaps, nr_maps * sizeof(*cximsd->xormaps));
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return 0;
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}
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static int test_random_params(void)
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{
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u8 valid_eiws[] = { 0, 1, 2, 3, 4, 8, 9, 10 };
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u16 valid_eigs[] = { 0, 1, 2, 3, 4, 5, 6 };
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int i, ways, pos, reverse_pos;
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u64 dpa, hpa, reverse_dpa;
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int iterations = 10000;
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int failures = 0;
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for (i = 0; i < iterations; i++) {
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/* Generate valid random parameters for eiw, eig, pos, dpa */
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u8 eiw = valid_eiws[get_random_u32() % ARRAY_SIZE(valid_eiws)];
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u16 eig = valid_eigs[get_random_u32() % ARRAY_SIZE(valid_eigs)];
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eiw_to_ways(eiw, &ways);
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pos = get_random_u32() % ways;
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dpa = get_random_u64() >> 12;
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reverse_dpa = ULLONG_MAX;
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reverse_pos = -1;
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hpa = cxl_calculate_hpa_offset(dpa, pos, eiw, eig);
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if (hpa != ULLONG_MAX) {
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reverse_dpa = cxl_calculate_dpa_offset(hpa, eiw, eig);
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reverse_pos = cxl_calculate_position(hpa, eiw, eig);
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if (reverse_dpa == dpa && reverse_pos == pos)
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continue;
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}
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pr_err("test random iter %d FAIL hpa=%llu, dpa=%llu reverse_dpa=%llu, pos=%d reverse_pos=%d eiw=%u eig=%u\n",
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i, hpa, dpa, reverse_dpa, pos, reverse_pos, eiw, eig);
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if (failures++ > 10) {
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pr_err("test random too many failures, stop\n");
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break;
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}
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}
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pr_info("..... test random: PASS %d FAIL %d\n", i - failures, failures);
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if (failures)
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return -EINVAL;
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return 0;
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}
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struct param_test {
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u8 eiw;
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u16 eig;
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int pos;
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bool expect; /* true: expect pass, false: expect fail */
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const char *desc;
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};
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static struct param_test param_tests[] = {
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{ 0x0, 0, 0, true, "1-way, min eig=0, pos=0" },
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{ 0x0, 3, 0, true, "1-way, mid eig=3, pos=0" },
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{ 0x0, 6, 0, true, "1-way, max eig=6, pos=0" },
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{ 0x1, 0, 0, true, "2-way, eig=0, pos=0" },
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{ 0x1, 3, 1, true, "2-way, eig=3, max pos=1" },
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{ 0x1, 6, 1, true, "2-way, eig=6, max pos=1" },
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{ 0x2, 0, 0, true, "4-way, eig=0, pos=0" },
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{ 0x2, 3, 3, true, "4-way, eig=3, max pos=3" },
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{ 0x2, 6, 3, true, "4-way, eig=6, max pos=3" },
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{ 0x3, 0, 0, true, "8-way, eig=0, pos=0" },
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{ 0x3, 3, 7, true, "8-way, eig=3, max pos=7" },
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{ 0x3, 6, 7, true, "8-way, eig=6, max pos=7" },
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{ 0x4, 0, 0, true, "16-way, eig=0, pos=0" },
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{ 0x4, 3, 15, true, "16-way, eig=3, max pos=15" },
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{ 0x4, 6, 15, true, "16-way, eig=6, max pos=15" },
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{ 0x8, 0, 0, true, "3-way, eig=0, pos=0" },
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{ 0x8, 3, 2, true, "3-way, eig=3, max pos=2" },
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{ 0x8, 6, 2, true, "3-way, eig=6, max pos=2" },
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{ 0x9, 0, 0, true, "6-way, eig=0, pos=0" },
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{ 0x9, 3, 5, true, "6-way, eig=3, max pos=5" },
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{ 0x9, 6, 5, true, "6-way, eig=6, max pos=5" },
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{ 0xA, 0, 0, true, "12-way, eig=0, pos=0" },
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{ 0xA, 3, 11, true, "12-way, eig=3, max pos=11" },
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{ 0xA, 6, 11, true, "12-way, eig=6, max pos=11" },
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{ 0x5, 0, 0, false, "invalid eiw=5" },
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{ 0x7, 0, 0, false, "invalid eiw=7" },
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{ 0xB, 0, 0, false, "invalid eiw=0xB" },
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{ 0xFF, 0, 0, false, "invalid eiw=0xFF" },
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{ 0x1, 7, 0, false, "invalid eig=7 (out of range)" },
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{ 0x2, 0x10, 0, false, "invalid eig=0x10" },
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{ 0x3, 0xFFFF, 0, false, "invalid eig=0xFFFF" },
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{ 0x1, 0, -1, false, "pos < 0" },
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{ 0x1, 0, 2, false, "2-way, pos=2 (>= ways)" },
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{ 0x2, 0, 4, false, "4-way, pos=4 (>= ways)" },
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{ 0x3, 0, 8, false, "8-way, pos=8 (>= ways)" },
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{ 0x4, 0, 16, false, "16-way, pos=16 (>= ways)" },
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{ 0x8, 0, 3, false, "3-way, pos=3 (>= ways)" },
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{ 0x9, 0, 6, false, "6-way, pos=6 (>= ways)" },
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{ 0xA, 0, 12, false, "12-way, pos=12 (>= ways)" },
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};
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static int test_cxl_validate_translation_params(void)
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{
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int i, rc, failures = 0;
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bool valid;
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for (i = 0; i < ARRAY_SIZE(param_tests); i++) {
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struct param_test *t = ¶m_tests[i];
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rc = cxl_validate_translation_params(t->eiw, t->eig, t->pos);
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valid = (rc == 0);
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if (valid != t->expect) {
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pr_err("test params failed: %s\n", t->desc);
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failures++;
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}
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}
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pr_info("..... test params: PASS %d FAIL %d\n", i - failures, failures);
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if (failures)
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return -EINVAL;
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return 0;
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}
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/*
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* cxl_translate_init
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*
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* Run the internal validation tests when no params are passed.
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* Otherwise, parse the parameters (test vectors), and kick off
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* the translation test.
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*
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* Returns: 0 on success, negative error code on failure
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*/
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static int __init cxl_translate_init(void)
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{
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int rc, i;
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/* If no tables are passed, validate module params only */
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if (table_num == 0) {
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pr_info("Internal validation test start...\n");
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rc = test_cxl_validate_translation_params();
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if (rc)
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return rc;
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rc = test_random_params();
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if (rc)
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return rc;
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pr_info("Internal validation test completed successfully\n");
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return 0;
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}
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pr_info("CXL translate test module loaded with %d test vectors\n",
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table_num);
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rc = setup_xor_mapping();
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if (rc)
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return rc;
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/* Process each test vector */
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for (i = 0; i < table_num; i++) {
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u64 dpa, expect_spa;
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int pos, math;
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u8 r_eiw, hb_ways;
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u16 r_eig;
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pr_debug("Processing test vector %d: '%s'\n", i, table[i]);
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/* Parse the test vector */
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rc = parse_test_vector(table[i], &dpa, &pos, &r_eiw, &r_eig,
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&hb_ways, &math, &expect_spa);
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if (rc) {
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pr_err("CXL Translate Test %d: FAIL\n"
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" Failed to parse test vector '%s'\n",
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i, table[i]);
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continue;
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}
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/* Run the translation test */
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rc = run_translation_test(dpa, pos, r_eiw, r_eig, hb_ways, math,
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expect_spa);
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if (rc) {
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pr_err("CXL Translate Test %d: FAIL\n"
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" dpa=%llu pos=%d r_eiw=%u r_eig=%u hb_ways=%u math=%s expect_spa=%llu\n",
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i, dpa, pos, r_eiw, r_eig, hb_ways,
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(math == XOR_MATH) ? "XOR" : "MODULO",
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expect_spa);
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} else {
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pr_info("CXL Translate Test %d: PASS\n", i);
|
|
}
|
|
}
|
|
|
|
kfree(cximsd);
|
|
pr_info("CXL translate test completed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit cxl_translate_exit(void)
|
|
{
|
|
pr_info("CXL translate test module unloaded\n");
|
|
}
|
|
|
|
module_param_array(table, charp, &table_num, 0444);
|
|
MODULE_PARM_DESC(table, "Test vectors as space-separated decimal strings");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("cxl_test: cxl address translation test module");
|
|
MODULE_IMPORT_NS("CXL");
|
|
|
|
module_init(cxl_translate_init);
|
|
module_exit(cxl_translate_exit);
|