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0c1f5e6e7b
The byte-map controls ("Byte Map N") already expose a value range of
[0, 256] to userspace via SOC_SINGLE_EXT(), where 256 is the
"disabled" sentinel. The driver stored this state as a byte-packed
u32 map[] array plus a separate byte_mask[] bitmap tracking which
slots were enabled, because 256 does not fit in a byte. As a result
get_byte_map() had to consult byte_mask[] to decide whether to
report the stored byte or 256, and put_byte_map() had to keep the
two arrays in sync on every write.
Store each slot as a u16 holding the control value directly
(0..255 enabled, 256 disabled). This is the native representation
for what userspace already sees, so get_byte_map() becomes a direct
return and put_byte_map() becomes a compare-and-store. The
hardware-facing packed RAM word and the IN_BYTE_EN mask are now
derived on the fly inside tegra210_adx_write_map_ram() from the
slot array, which is the only place that needs to know about the
hardware layout.
The byte_mask buffer is allocated in probe() using devm_kcalloc()
with soc_data->byte_mask_size, so it scales to any SoC variant
without depending on chip-specific constants. It is zeroed and
recomputed each time write_map_ram() is called.
A new TEGRA_ADX_SLOTS_PER_WORD constant replaces the literal '4'
used for byte slots per RAM word, and BITS_PER_BYTE /
BITS_PER_TYPE() from <linux/bits.h> replace the literal '8' and
'32' shifts.
Slots are initialised to 256 in probe() so the default reported
value stays "disabled", matching previous behaviour. Values written
from userspace that fall outside [0, 255] are clamped to 256
("disabled") exactly as before -- no userspace-visible change.
As a side effect this also fixes a latent bug in the previous
put_byte_map(): because it compared the enable mask rather than the
stored byte, changing a slot from one enabled value to another
enabled value (e.g. 42 -> 99) would early-return without persisting
the new value, and the next CFG_RAM flush would still program the
old byte. The new implementation compares the stored value itself,
so this case is now handled correctly.
Addresses TODO left in tegra210_adx_get_byte_map().
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
Link: https://patch.msgid.link/20260410200530.171323-2-piyushpatle228@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved.
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*
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* tegra210_adx.h - Definitions for Tegra210 ADX driver
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*
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*/
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#ifndef __TEGRA210_ADX_H__
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#define __TEGRA210_ADX_H__
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#include <linux/types.h>
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/* Register offsets from TEGRA210_ADX*_BASE */
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#define TEGRA210_ADX_RX_STATUS 0x0c
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#define TEGRA210_ADX_RX_INT_STATUS 0x10
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#define TEGRA210_ADX_RX_INT_MASK 0x14
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#define TEGRA210_ADX_RX_INT_SET 0x18
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#define TEGRA210_ADX_RX_INT_CLEAR 0x1c
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#define TEGRA210_ADX_RX_CIF_CTRL 0x20
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#define TEGRA210_ADX_TX_STATUS 0x4c
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#define TEGRA210_ADX_TX_INT_STATUS 0x50
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#define TEGRA210_ADX_TX_INT_MASK 0x54
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#define TEGRA210_ADX_TX_INT_SET 0x58
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#define TEGRA210_ADX_TX_INT_CLEAR 0x5c
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#define TEGRA210_ADX_TX1_CIF_CTRL 0x60
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#define TEGRA210_ADX_TX2_CIF_CTRL 0x64
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#define TEGRA210_ADX_TX3_CIF_CTRL 0x68
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#define TEGRA210_ADX_TX4_CIF_CTRL 0x6c
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#define TEGRA210_ADX_ENABLE 0x80
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#define TEGRA210_ADX_SOFT_RESET 0x84
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#define TEGRA210_ADX_CG 0x88
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#define TEGRA210_ADX_STATUS 0x8c
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#define TEGRA210_ADX_INT_STATUS 0x90
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#define TEGRA210_ADX_CTRL 0xa4
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#define TEGRA210_ADX_IN_BYTE_EN0 0xa8
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#define TEGRA210_ADX_IN_BYTE_EN1 0xac
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#define TEGRA210_ADX_CFG_RAM_CTRL 0xb8
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#define TEGRA210_ADX_CFG_RAM_DATA 0xbc
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#define TEGRA264_ADX_CYA 0xb8
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#define TEGRA264_ADX_CFG_RAM_CTRL 0xc0
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#define TEGRA264_ADX_CFG_RAM_DATA 0xc4
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/* Fields in TEGRA210_ADX_ENABLE */
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#define TEGRA210_ADX_ENABLE_SHIFT 0
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/* Fields in TEGRA210_ADX_CFG_RAM_CTRL */
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#define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0
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#define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14
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#define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT)
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#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
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/* Fields in TEGRA210_ADX_SOFT_RESET */
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#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0
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#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
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#define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
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#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
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#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4
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#define TEGRA_ADX_SLOTS_PER_WORD 4
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#define TEGRA210_ADX_RAM_DEPTH 16
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#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6
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#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2
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#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0
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#define TEGRA210_ADX_BYTE_MASK_COUNT 2
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#define TEGRA210_ADX_MAX_CHANNEL 16
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#define TEGRA210_ADX_CYA_OFFSET 0
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#define TEGRA264_ADX_RAM_DEPTH 32
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#define TEGRA264_ADX_BYTE_MASK_COUNT 4
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#define TEGRA264_ADX_MAX_CHANNEL 32
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#define TEGRA264_ADX_CYA_OFFSET 8
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#define TEGRA_ADX_IN_DAI_ID 4
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struct tegra210_adx_soc_data {
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const struct regmap_config *regmap_conf;
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const struct snd_kcontrol_new *controls;
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unsigned int num_controls;
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unsigned int max_ch;
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unsigned int ram_depth;
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unsigned int byte_mask_size;
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unsigned int cya_offset;
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};
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struct tegra210_adx {
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struct regmap *regmap;
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unsigned int *byte_mask;
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u16 *map;
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const struct tegra210_adx_soc_data *soc_data;
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};
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#endif
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