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Add support for Anbernic's RG-DS audio amplifiers, powered by Awinic AW87391 amplifier ICs. These chips typically require an init sequence provided by firmware, but the manufacturer did not provide firmware in this case. As a result we had to hard-code the init sequence and use a device specific binding (rather than a binding just for the aw87391). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://patch.msgid.link/20260128174608.1498-3-macroalpha82@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
172 lines
4.8 KiB
C
172 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// aw87390.h -- aw87390 ALSA SoC Audio driver
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//
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// Copyright (c) 2023 awinic Technology CO., LTD
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//
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// Author: Weidong Wang <wangweidong.a@awinic.com>
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//
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#ifndef __AW87390_H__
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#define __AW87390_H__
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#define AW87390_ID_REG (0x00)
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#define AW87390_SYSCTRL_REG (0x01)
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#define AW87390_MDCTRL_REG (0x02)
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#define AW87390_CPOVP_REG (0x03)
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#define AW87390_CPP_REG (0x04)
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#define AW87390_PAG_REG (0x05)
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#define AW87390_AGC3P_REG (0x06)
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#define AW87390_AGC3PA_REG (0x07)
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#define AW87390_AGC2P_REG (0x08)
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#define AW87390_AGC2PA_REG (0x09)
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#define AW87390_AGC1PA_REG (0x0A)
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#define AW87390_SYSST_REG (0x59)
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#define AW87390_SYSINT_REG (0x60)
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#define AW87390_DFT_SYSCTRL_REG (0x61)
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#define AW87390_DFT_MDCTRL_REG (0x62)
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#define AW87390_DFT_CPADP_REG (0x63)
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#define AW87390_DFT_AGCPA_REG (0x64)
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#define AW87390_DFT_POFR_REG (0x65)
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#define AW87390_DFT_OC_REG (0x66)
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#define AW87390_DFT_ADP1_REG (0x67)
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#define AW87390_DFT_REF_REG (0x68)
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#define AW87390_DFT_LDO_REG (0x69)
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#define AW87390_ADP1_REG (0x70)
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#define AW87390_ADP2_REG (0x71)
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#define AW87390_NG1_REG (0x72)
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#define AW87390_NG2_REG (0x73)
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#define AW87390_NG3_REG (0x74)
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#define AW87390_CP_REG (0x75)
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#define AW87390_AB_REG (0x76)
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#define AW87390_TEST_REG (0x77)
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#define AW87390_ENCR_REG (0x78)
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#define AW87390_DELAY_REG_ADDR (0xFE)
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#define AW87390_SOFT_RESET_VALUE (0xAA)
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#define AW87390_POWER_DOWN_VALUE (0x00)
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#define AW87390_REG_MAX (0xFF)
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#define AW87390_DEV_DEFAULT_CH (0)
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#define AW87390_INIT_PROFILE (0)
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#define AW87390_REG_DELAY_TIME (1000)
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#define AW87390_I2C_NAME "aw87390"
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#define AW87390_ACF_FILE "aw87390_acf.bin"
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#define AW87391_SYSCTRL_REG (0x01)
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#define AW87391_REG_VER_SEL_LOW (0 << 6)
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#define AW87391_REG_VER_SEL_NORMAL (1 << 6)
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#define AW87391_REG_VER_SEL_SUPER (2 << 6)
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#define AW87391_REG_EN_ADAP BIT(5)
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#define AW87391_REG_EN_2X BIT(4)
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#define AW87391_EN_SPK BIT(3)
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#define AW87391_EN_PA BIT(2)
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#define AW87391_REG_EN_CP BIT(1)
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#define AW87391_EN_SW BIT(0)
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#define AW87391_CP_REG (0x02)
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#define AW87391_REG_CP_OVP_6_50V 0
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#define AW87391_REG_CP_OVP_6_75V 1
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#define AW87391_REG_CP_OVP_7_00V 2
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#define AW87391_REG_CP_OVP_7_25V 3
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#define AW87391_REG_CP_OVP_7_50V 4
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#define AW87391_REG_CP_OVP_7_75V 5
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#define AW87391_REG_CP_OVP_8_00V 6
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#define AW87391_REG_CP_OVP_8_25V 7
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#define AW87391_REG_CP_OVP_8_50V 8
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#define AW87391_PAG_REG (0x03)
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#define AW87391_GAIN_12DB 0
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#define AW87391_GAIN_15DB 1
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#define AW87391_GAIN_18DB 2
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#define AW87391_GAIN_21DB 3
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#define AW87391_GAIN_24DB 4
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#define AW87391_AGCPO_REG (0x04)
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#define AW87391_AK1_S_016 (2 << 5)
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#define AW87391_AK1_S_032 (3 << 5)
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#define AW87391_PD_AGC1_PWRDN BIT(4)
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/* AGC2PO supports values between 500mW (0000) to 1600mW (1011) */
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#define AW87391_AGC2PO_MW(n) ((n / 100) - 5)
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#define AW87391_AGC2PA_REG (0x05)
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#define AW87391_RK_S_5_12 (0 << 5)
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#define AW87391_RK_S_10_24 (1 << 5)
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#define AW87391_RK_S_20_48 (2 << 5)
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#define AW87391_RK_S_41 (3 << 5)
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#define AW87391_RK_S_82 (4 << 5)
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#define AW87391_RK_S_164 (5 << 5)
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#define AW87391_RK_S_328 (6 << 5)
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#define AW87391_RK_S_656 (7 << 5)
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#define AW87391_AK2_S_1_28 (0 << 2)
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#define AW87391_AK2_S_2_56 (1 << 2)
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#define AW87391_AK2_S_10_24 (2 << 2)
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#define AW87391_AK2_S_41 (3 << 2)
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#define AW87391_AK2_S_82 (4 << 2)
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#define AW87391_AK2_S_164 (5 << 2)
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#define AW87391_AK2_S_328 (6 << 2)
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#define AW87391_AK2_S_656 (7 << 2)
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#define AW87391_AK2F_S_10_24 0
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#define AW87391_AK2F_S_20_48 1
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#define AW87391_AK2F_S_41 2
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#define AW87391_AK2F_S_82 3
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#define AW87391_SYSST_REG (0x06)
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#define AW87391_UVLO BIT(7)
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#define AW87391_OTN BIT(6)
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#define AW87391_OC_FLAG BIT(5)
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#define AW87391_ADAP_CP BIT(4)
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#define AW87391_STARTOK BIT(3)
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#define AW87391_CP_OVP BIT(2)
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#define AW87391_PORN BIT(1)
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#define AW87391_SYSINT_REG (0x07)
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#define AW87391_UVLOI BIT(7)
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#define AW87391_ONTI BIT(6)
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#define AW87391_OC_FLAGI BIT(5)
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#define AW87391_ADAP_CPI BIT(4)
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#define AW87391_STARTOKI BIT(3)
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#define AW87391_CP_OVPI BIT(2)
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#define AW87391_PORNI BIT(1)
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#define AW87391_DFT_THGEN0_REG (0x63)
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#define AW87391_ADAPVTH_01W (0 << 2)
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#define AW87391_ADAPVTH_02W (1 << 2)
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#define AW87391_ADAPVTH_03W (2 << 2)
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#define AW87391_ADAPVTH_04W (3 << 2)
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#define AW87391_I2C_NAME "aw87391"
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#define AW87390_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
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.name = xname, \
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.info = profile_info, \
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.get = profile_get, \
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.put = profile_set, \
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}
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enum aw87390_id {
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AW87390_CHIP_ID = 0x76,
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AW87391_CHIP_ID = 0xc1,
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};
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enum {
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AW87390_DEV_FW_FAILED = 0,
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AW87390_DEV_FW_OK,
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};
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enum {
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AW87390_DEV_PW_OFF = 0,
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AW87390_DEV_PW_ON,
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};
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struct aw87390 {
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struct aw_device *aw_pa;
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struct mutex lock;
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struct regmap *regmap;
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struct aw_container *aw_cfg;
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struct regulator *vdd_reg;
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};
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#endif
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