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06c990bffd
Add the RK3588_SYSGRF_SOC_CON6 register offset to the RK3588 GRF header. This register contains the I2S MCLK output to IO gate bits, needed by the clock driver. Signed-off-by: Daniele Briguglio <hello@superkali.me> Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://patch.msgid.link/20260419-rk3588-mclk-gate-grf-v4-4-513a42dd1dcc@superkali.me Signed-off-by: Heiko Stuebner <heiko@sntech.de>
25 lines
926 B
C
25 lines
926 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __SOC_RK3588_GRF_H
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#define __SOC_RK3588_GRF_H
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#define RK3588_PMUGRF_OS_REG2 0x208
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#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
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#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
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#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
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#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
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#define RK3588_PMUGRF_OS_REG3 0x20c
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#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
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#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
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#define RK3588_PMUGRF_OS_REG4 0x210
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#define RK3588_PMUGRF_OS_REG5 0x214
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#define RK3588_PMUGRF_OS_REG6 0x218
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#define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE GENMASK(2, 1)
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/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
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#define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0)
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#define RK3588_SYSGRF_SOC_CON6 0x0318
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#endif /* __SOC_RK3588_GRF_H */
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