mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-29 04:34:45 -04:00
7b78fa8622
The output pixel interface is a parallel bus (32 bits), which supports sending multiple pixels (1, 2 or 4) per clock cycle for smaller pixel widths like RAW8-RAW16. Dual-pixel and Quad-pixel modes can be a requirement if the export rate of the Cadence IP in Single-pixel mode maxes out before the maximum supported DPHY-RX frequency, which is the case with TI's integration of this IP [1]. So, we export a function that lets the downstream hardware block request a higher pixel-per-clock on a particular output pad. We check if we can support the requested pixels per clock given the known maximum for the currently configured format. If not, we set it to the highest feasible value and return this value to the caller. [1] Section 12.6.1.4.8.14 CSI_RX_IF Programming Restrictions of AM62 TRM Link: https://www.ti.com/lit/pdf/spruj16 Tested-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> (on SK-AM68) Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
20 lines
500 B
C
20 lines
500 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
#ifndef _CDNS_CSI2RX_H
|
|
#define _CDNS_CSI2RX_H
|
|
|
|
#include <media/v4l2-subdev.h>
|
|
|
|
/**
|
|
* cdns_csi2rx_negotiate_ppc - Negotiate pixel-per-clock on output interface
|
|
*
|
|
* @subdev: point to &struct v4l2_subdev
|
|
* @pad: pad number of the source pad
|
|
* @ppc: pointer to requested pixel-per-clock value
|
|
*
|
|
* Returns 0 on success, negative error code otherwise.
|
|
*/
|
|
int cdns_csi2rx_negotiate_ppc(struct v4l2_subdev *subdev, unsigned int pad,
|
|
u8 *ppc);
|
|
|
|
#endif
|