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dee49a1860
Add a new compatible for the External Memory Interface Interconnect found on the MediaTek MT8196 Chromebook SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20251124-mt8196-dvfsrc-v2-3-d9c1334db9f3@collabora.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8196_H
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#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8196_H
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#define SLAVE_DDR_EMI 0
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#define MASTER_MCUSYS 1
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#define MASTER_MCU_0 2
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#define MASTER_MCU_1 3
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#define MASTER_MCU_2 4
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#define MASTER_MCU_3 5
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#define MASTER_MCU_4 6
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#define MASTER_GPUSYS 7
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#define MASTER_MMSYS 8
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#define MASTER_MM_VPU 9
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#define MASTER_MM_DISP 10
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#define MASTER_MM_VDEC 11
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#define MASTER_MM_VENC 12
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#define MASTER_MM_CAM 13
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#define MASTER_MM_IMG 14
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#define MASTER_MM_MDP 15
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#define MASTER_VPUSYS 16
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#define MASTER_VPU_0 17
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#define MASTER_VPU_1 18
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#define MASTER_MDLASYS 19
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#define MASTER_MDLA_0 20
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#define MASTER_UFS 21
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#define MASTER_PCIE 22
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#define MASTER_USB 23
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#define MASTER_WIFI 24
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#define MASTER_BT 25
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#define MASTER_NETSYS 26
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#define MASTER_DBGIF 27
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#define SLAVE_HRT_DDR_EMI 28
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#define MASTER_HRT_MMSYS 29
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#define MASTER_HRT_MM_DISP 30
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#define MASTER_HRT_MM_VDEC 31
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#define MASTER_HRT_MM_VENC 32
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#define MASTER_HRT_MM_CAM 33
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#define MASTER_HRT_MM_IMG 34
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#define MASTER_HRT_MM_MDP 35
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#define MASTER_HRT_ADSP 36
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#define MASTER_HRT_DBGIF 37
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#endif
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