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fc6e29d428
The MDSS resets have so far been left undescribed. Fix that.
Fixes: 75616da712 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
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/* Clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_PLL0_OUT_EVEN 1
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#define DISP_CC_MDSS_AHB_CLK 2
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#define DISP_CC_MDSS_AHB_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_CLK 4
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
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#define DISP_CC_MDSS_DP_AUX_CLK 8
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9
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#define DISP_CC_MDSS_DP_CRYPTO_CLK 10
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#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11
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#define DISP_CC_MDSS_DP_LINK_CLK 12
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
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#define DISP_CC_MDSS_DP_PIXEL_CLK 16
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
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#define DISP_CC_MDSS_ESC0_CLK 18
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#define DISP_CC_MDSS_ESC0_CLK_SRC 19
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#define DISP_CC_MDSS_MDP_CLK 20
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#define DISP_CC_MDSS_MDP_CLK_SRC 21
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#define DISP_CC_MDSS_MDP_LUT_CLK 22
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
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#define DISP_CC_MDSS_PCLK0_CLK 24
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 25
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#define DISP_CC_MDSS_ROT_CLK 26
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#define DISP_CC_MDSS_ROT_CLK_SRC 27
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#define DISP_CC_MDSS_RSCC_AHB_CLK 28
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
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#define DISP_CC_MDSS_VSYNC_CLK 30
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
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#define DISP_CC_XO_CLK 32
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/* Resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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/* GDSCs */
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#define MDSS_GDSC 0
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#endif
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