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c17ccefb61
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
19 lines
442 B
C
19 lines
442 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
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#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
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#define APCS_ALIAS0_CLK_SRC 0
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#define APCS_ALIAS0_CORE_CLK 1
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#define APSS_PLL_EARLY 2
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#define APSS_SILVER_CLK_SRC 3
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#define APSS_SILVER_CORE_CLK 4
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#define L3_PLL 5
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#define L3_CLK_SRC 6
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#define L3_CORE_CLK 7
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#endif
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