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This patch introduces support for the Cadence USBSSP (cdnsp) controller in hardware configurations where the Dual-Role Device (DRD) register block is not implemented or is inaccessible. In such cases, the driver cannot rely on the DRD logic to manage roles and must operate exclusively in a fixed peripheral/host mode. The change in BAR indexing (from BAR 2 to BAR 1) is a direct consequence of the 32-bit addressing used in this specific DRD-disabled hardware layout, compared to the 64-bit addressing used in DRD-enabled configurations. Tested on a PCI platform with a hardware configuration that lacks DRD support. Platform-side changes are included to support the PCI glue layer's property injection to handle this specific layout. Acked-by: Peter Chen <peter.chen@kernel.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Pawel Laszczak <pawell@cadence.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202605141023.18vWXyw3-lkp@intel.com/ Link: Closes: https://lore.kernel.org/oe-kbuild-all/202605141023.18vWXyw3-lkp@intel.com/ Link: https://patch.msgid.link/20260521-no_drd_config_v9-v9-2-2512cef10104@cadence.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
248 lines
6.8 KiB
C
248 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Cadence USBSSP PCI Glue driver.
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*
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* Copyright (C) 2019 Cadence.
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*
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* Author: Pawel Laszczak <pawell@cadence.com>
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include "core.h"
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struct cdnsp_wrap {
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struct platform_device *plat_dev;
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struct property_entry prop[3];
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struct resource dev_res[6];
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int devfn;
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};
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#define RES_IRQ_HOST_ID 0
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#define RES_IRQ_PERIPHERAL_ID 1
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#define RES_IRQ_OTG_ID 2
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#define RES_HOST_ID 3
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#define RES_DEV_ID 4
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#define RES_DRD_ID 5
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/* DRD PCI configuration - 64-bit addressing */
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/* First PCI function */
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#define PCI_BAR_HOST 0
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#define PCI_BAR_DEV 2
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/* Second PCI function */
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#define PCI_BAR_OTG 0
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/* Device only PCI configuration - 32-bit addressing */
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/* First PCI function */
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#define PCI_BAR_ONLY_DEV 1
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#define PCI_DEV_FN_HOST_DEVICE 0
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#define PCI_DEV_FN_OTG 1
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#define PCI_DRIVER_NAME "cdns-pci-usbssp"
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#define PLAT_DRIVER_NAME "cdns-usb3"
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#define PCI_DEVICE_ID_CDNS_UDC_USBSSP 0x0400
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#define CHICKEN_APB_TIMEOUT_VALUE 0x1C20
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static struct pci_dev *cdnsp_get_second_fun(struct pci_dev *pdev)
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{
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/*
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* Gets the second function.
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* Platform has two function. The first keeps resources for
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* Host/Device while the second keeps resources for DRD/OTG.
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*/
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if (pdev->device == PCI_DEVICE_ID_CDNS_USBSSP)
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return pci_get_device(pdev->vendor, PCI_DEVICE_ID_CDNS_USBSS, NULL);
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if (pdev->device == PCI_DEVICE_ID_CDNS_USBSS)
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return pci_get_device(pdev->vendor, PCI_DEVICE_ID_CDNS_USBSSP, NULL);
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return NULL;
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}
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static int cdnsp_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct platform_device_info plat_info;
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static struct cdns3_platform_data pdata;
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struct cdnsp_wrap *wrap;
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struct resource *res;
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struct pci_dev *func;
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bool no_drd = false;
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int ret = 0;
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/*
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* For GADGET/HOST PCI (devfn) function number is 0,
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* for OTG PCI (devfn) function number is 1.
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*/
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if (!id || (pdev->devfn != PCI_DEV_FN_HOST_DEVICE &&
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pdev->devfn != PCI_DEV_FN_OTG))
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return -EINVAL;
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if (pdev->device == PCI_DEVICE_ID_CDNS_UDC_USBSSP)
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no_drd = true;
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func = cdnsp_get_second_fun(pdev);
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if (!func && !no_drd)
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return -EINVAL;
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if ((func && func->class == PCI_CLASS_SERIAL_USB_XHCI) ||
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pdev->class == PCI_CLASS_SERIAL_USB_XHCI) {
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ret = -EINVAL;
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goto put_pci;
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}
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ret = pcim_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "Enabling PCI device has failed %d\n", ret);
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goto put_pci;
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}
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pci_set_master(pdev);
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if (func && pci_is_enabled(func)) {
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wrap = pci_get_drvdata(func);
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} else {
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wrap = kzalloc_obj(*wrap);
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if (!wrap) {
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ret = -ENOMEM;
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goto put_pci;
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}
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}
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res = wrap->dev_res;
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if (pdev->devfn == PCI_DEV_FN_HOST_DEVICE) {
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int bar_dev = no_drd ? PCI_BAR_ONLY_DEV : PCI_BAR_DEV;
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/* Function 0: host(BAR_0) + device(BAR_2). */
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dev_dbg(&pdev->dev, "Initialize Device resources\n");
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res[RES_DEV_ID].start = pci_resource_start(pdev, bar_dev);
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res[RES_DEV_ID].end = pci_resource_end(pdev, bar_dev);
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res[RES_DEV_ID].name = "dev";
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res[RES_DEV_ID].flags = IORESOURCE_MEM;
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dev_dbg(&pdev->dev, "USBSSP-DEV physical base addr: %pa\n",
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&res[RES_DEV_ID].start);
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res[RES_HOST_ID].start = pci_resource_start(pdev, PCI_BAR_HOST);
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res[RES_HOST_ID].end = pci_resource_end(pdev, PCI_BAR_HOST);
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res[RES_HOST_ID].name = "xhci";
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res[RES_HOST_ID].flags = IORESOURCE_MEM;
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dev_dbg(&pdev->dev, "USBSSP-XHCI physical base addr: %pa\n",
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&res[RES_HOST_ID].start);
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/* Interrupt for XHCI */
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wrap->dev_res[RES_IRQ_HOST_ID].start = pdev->irq;
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wrap->dev_res[RES_IRQ_HOST_ID].name = "host";
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wrap->dev_res[RES_IRQ_HOST_ID].flags = IORESOURCE_IRQ;
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/* Interrupt for device. It's the same as for HOST. */
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wrap->dev_res[RES_IRQ_PERIPHERAL_ID].start = pdev->irq;
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wrap->dev_res[RES_IRQ_PERIPHERAL_ID].name = "peripheral";
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wrap->dev_res[RES_IRQ_PERIPHERAL_ID].flags = IORESOURCE_IRQ;
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} else {
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res[RES_DRD_ID].start = pci_resource_start(pdev, PCI_BAR_OTG);
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res[RES_DRD_ID].end = pci_resource_end(pdev, PCI_BAR_OTG);
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res[RES_DRD_ID].name = "otg";
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res[RES_DRD_ID].flags = IORESOURCE_MEM;
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dev_dbg(&pdev->dev, "CDNSP-DRD physical base addr: %pa\n",
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&res[RES_DRD_ID].start);
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/* Interrupt for OTG/DRD. */
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wrap->dev_res[RES_IRQ_OTG_ID].start = pdev->irq;
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wrap->dev_res[RES_IRQ_OTG_ID].name = "otg";
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wrap->dev_res[RES_IRQ_OTG_ID].flags = IORESOURCE_IRQ;
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}
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if (no_drd || pci_is_enabled(func)) {
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u8 idx = 0;
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/* set up platform device info */
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pdata.override_apb_timeout = CHICKEN_APB_TIMEOUT_VALUE;
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if (no_drd) {
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wrap->prop[idx++] = PROPERTY_ENTRY_STRING("compatible",
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"cdns,cdnsp");
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wrap->prop[idx++] = PROPERTY_ENTRY_STRING("dr_mode", "peripheral");
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} else {
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wrap->prop[idx++] = PROPERTY_ENTRY_STRING("dr_mode", "otg");
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wrap->prop[idx++] = PROPERTY_ENTRY_BOOL("usb-role-switch");
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}
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memset(&plat_info, 0, sizeof(plat_info));
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plat_info.parent = &pdev->dev;
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plat_info.fwnode = pdev->dev.fwnode;
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plat_info.name = PLAT_DRIVER_NAME;
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plat_info.id = pdev->devfn;
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plat_info.res = wrap->dev_res;
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plat_info.num_res = ARRAY_SIZE(wrap->dev_res);
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plat_info.dma_mask = pdev->dma_mask;
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plat_info.data = &pdata;
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plat_info.size_data = sizeof(pdata);
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plat_info.properties = wrap->prop;
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wrap->devfn = pdev->devfn;
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/* register platform device */
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wrap->plat_dev = platform_device_register_full(&plat_info);
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if (IS_ERR(wrap->plat_dev)) {
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ret = PTR_ERR(wrap->plat_dev);
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kfree(wrap);
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goto put_pci;
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}
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}
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pci_set_drvdata(pdev, wrap);
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put_pci:
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pci_dev_put(func);
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return ret;
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}
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static void cdnsp_pci_remove(struct pci_dev *pdev)
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{
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struct cdnsp_wrap *wrap;
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struct pci_dev *func;
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func = cdnsp_get_second_fun(pdev);
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wrap = pci_get_drvdata(pdev);
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if (wrap->devfn == pdev->devfn)
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platform_device_unregister(wrap->plat_dev);
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if (!func || !pci_is_enabled(func))
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kfree(wrap);
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pci_dev_put(func);
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}
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static const struct pci_device_id cdnsp_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CDNS, PCI_DEVICE_ID_CDNS_UDC_USBSSP),
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.class = PCI_CLASS_SERIAL_USB_DEVICE },
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{ PCI_DEVICE(PCI_VENDOR_ID_CDNS, PCI_DEVICE_ID_CDNS_UDC_USBSSP),
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.class = PCI_CLASS_SERIAL_USB_CDNS },
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{ PCI_DEVICE(PCI_VENDOR_ID_CDNS, PCI_DEVICE_ID_CDNS_USBSSP),
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.class = PCI_CLASS_SERIAL_USB_DEVICE },
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{ PCI_DEVICE(PCI_VENDOR_ID_CDNS, PCI_DEVICE_ID_CDNS_USBSSP),
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.class = PCI_CLASS_SERIAL_USB_CDNS },
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{ PCI_DEVICE(PCI_VENDOR_ID_CDNS, PCI_DEVICE_ID_CDNS_USBSS),
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.class = PCI_CLASS_SERIAL_USB_CDNS },
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{ 0, }
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};
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static struct pci_driver cdnsp_pci_driver = {
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.name = PCI_DRIVER_NAME,
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.id_table = cdnsp_pci_ids,
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.probe = cdnsp_pci_probe,
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.remove = cdnsp_pci_remove,
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};
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module_pci_driver(cdnsp_pci_driver);
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MODULE_DEVICE_TABLE(pci, cdnsp_pci_ids);
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MODULE_ALIAS("pci:cdnsp");
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MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Cadence CDNSP PCI wrapper");
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