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e075d77683
Build on the previously introduced TXC DPLL framework and implement
full TX reference clock control and hardware-backed synchronization
status reporting for E825 devices.
E825 firmware may accept or override TX reference clock requests based
on device-wide routing constraints and link conditions. Because the
final selection becomes visible only after a link-up event, the driver
splits the observation into two complementary signals:
- TXCLK pin state reflects the requested TX reference clock
(pf->ptp.port.tx_clk_req). After a link-up, the value is reconciled
against the SERDES reference selector by
ice_txclk_update_and_notify(); if firmware or auto-negotiation
selected a different clock, tx_clk_req is overwritten so that pin
state converges to the actual hardware selection.
- TXC DPLL lock status reflects hardware synchronization:
* LOCKED when an external TX reference is in use
* UNLOCKED when falling back to ENET/TXCO, or when a requested
external reference has not (yet) been accepted by hardware.
Userspace observing only pin state therefore sees user intent, while
lock status is the authoritative indicator of whether the requested
clock is actually selected and synchronizing. This matches the DPLL
subsystem model where pin state describes topology and device lock
status describes signal quality.
TX reference selection topology:
- External references (SYNCE, EREF0) are represented as TXCLK pins
- The internal ENET/TXCO clock has no pin representation; when
selected, all TXCLK pins are reported DISCONNECTED
With this change, TX reference clocks on E825 devices can be reliably
selected, observed via standard DPLL interfaces, and monitored for
effective synchronization through TXC DPLL lock status.
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Link: https://patch.msgid.link/20260607183045.1213735-14-grzegorz.nitka@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2026 Intel Corporation */
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#ifndef _ICE_TXCLK_H_
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#define _ICE_TXCLK_H_
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/**
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* ice_txclk_any_port_uses - check if any port on a PHY uses this TX refclk
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* @ctrl_pf: control PF (owner of the shared tx_refclks map)
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* @phy: PHY index
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* @clk: TX reference clock
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*
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* Return: true if any bit (port) is set for this clock on this PHY
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*/
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static inline bool
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ice_txclk_any_port_uses(const struct ice_pf *ctrl_pf, u8 phy,
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enum ice_e825c_ref_clk clk)
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{
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return find_first_bit(&ctrl_pf->ptp.tx_refclks[phy][clk],
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BITS_PER_LONG) < BITS_PER_LONG;
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}
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static inline enum dpll_lock_status
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ice_txclk_lock_status(enum ice_e825c_ref_clk clk)
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{
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switch (clk) {
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case ICE_REF_CLK_SYNCE:
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case ICE_REF_CLK_EREF0:
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return DPLL_LOCK_STATUS_LOCKED;
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case ICE_REF_CLK_ENET:
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default:
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return DPLL_LOCK_STATUS_UNLOCKED;
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}
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}
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int ice_txclk_set_clk(struct ice_pf *pf, enum ice_e825c_ref_clk clk);
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void ice_txclk_update_and_notify(struct ice_pf *pf);
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struct dpll_pin *ice_txclk_get_pin(struct ice_pf *pf,
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enum ice_e825c_ref_clk ref_clk);
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#endif /* _ICE_TXCLK_H_ */
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