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4405938293
Production PVC hardware had a graphics stepping of C0. Xe1 platforms already aren't officially supported by the Xe driver, but pre-production steppings are especially out of scope (and 'has_pre_prod_wa' is not set in the device descriptor). Drop the workarounds that aren't relevant to production hardware. v2: - Drop the stream->override_gucrc which is no longer set anywhere after the removal of Wa_1509372804. (Bala) - Drop xe_guc_rc_set_mode / xe_guc_rc_unset_mode which are no longer used after the removal of Wa_1509372804. Bspec: 44484 Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-2-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2026 Intel Corporation
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*/
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#include <drm/drm_print.h>
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#include "abi/guc_actions_slpc_abi.h"
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#include "xe_device.h"
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#include "xe_force_wake.h"
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#include "xe_gt.h"
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#include "xe_gt_idle.h"
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#include "xe_gt_printk.h"
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#include "xe_guc.h"
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#include "xe_guc_ct.h"
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#include "xe_guc_pc.h"
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#include "xe_guc_rc.h"
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#include "xe_pm.h"
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/**
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* DOC: GuC RC (Render C-states)
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*
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* GuC handles the GT transition to deeper C-states in conjunction with Pcode.
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* GuC RC can be enabled independently of the frequency component in SLPC,
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* which is also controlled by GuC.
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*
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* This file will contain all H2G related logic for handling Render C-states.
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* There are some calls to xe_gt_idle, where we enable host C6 when GuC RC is
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* skipped. GuC RC is mostly independent of xe_guc_pc with the exception of
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* functions that override the mode for which we have to rely on the SLPC H2G
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* calls.
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*/
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static int guc_action_setup_gucrc(struct xe_guc *guc, u32 control)
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{
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u32 action[] = {
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GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
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control,
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};
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int ret;
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ret = xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
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if (ret && !(xe_device_wedged(guc_to_xe(guc)) && ret == -ECANCELED))
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xe_gt_err(guc_to_gt(guc),
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"GuC RC setup %s(%u) failed (%pe)\n",
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control == GUCRC_HOST_CONTROL ? "HOST_CONTROL" :
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control == GUCRC_FIRMWARE_CONTROL ? "FIRMWARE_CONTROL" :
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"UNKNOWN", control, ERR_PTR(ret));
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return ret;
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}
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/**
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* xe_guc_rc_disable() - Disable GuC RC
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* @guc: Xe GuC instance
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*
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* Disables GuC RC by taking control of RC6 back from GuC.
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*/
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void xe_guc_rc_disable(struct xe_guc *guc)
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{
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struct xe_device *xe = guc_to_xe(guc);
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struct xe_gt *gt = guc_to_gt(guc);
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if (!xe->info.skip_guc_pc && xe->info.platform != XE_PVC)
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if (guc_action_setup_gucrc(guc, GUCRC_HOST_CONTROL))
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return;
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xe_gt_WARN_ON(gt, xe_gt_idle_disable_c6(gt));
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}
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static void xe_guc_rc_fini_hw(void *arg)
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{
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struct xe_guc *guc = arg;
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struct xe_device *xe = guc_to_xe(guc);
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struct xe_gt *gt = guc_to_gt(guc);
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if (xe_device_wedged(xe))
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return;
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CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
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xe_guc_rc_disable(guc);
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}
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/**
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* xe_guc_rc_init() - Init GuC RC
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* @guc: Xe GuC instance
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*
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* Add callback action for GuC RC
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*
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* Return: 0 on success, negative error code on error.
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*/
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int xe_guc_rc_init(struct xe_guc *guc)
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{
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struct xe_device *xe = guc_to_xe(guc);
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struct xe_gt *gt = guc_to_gt(guc);
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xe_gt_assert(gt, xe_device_uc_enabled(xe));
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return devm_add_action_or_reset(xe->drm.dev, xe_guc_rc_fini_hw, guc);
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}
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/**
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* xe_guc_rc_enable() - Enable GuC RC feature if applicable
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* @guc: Xe GuC instance
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*
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* Enables GuC RC feature.
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*
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* Return: 0 on success, negative error code on error.
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*/
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int xe_guc_rc_enable(struct xe_guc *guc)
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{
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struct xe_device *xe = guc_to_xe(guc);
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struct xe_gt *gt = guc_to_gt(guc);
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xe_gt_assert(gt, xe_device_uc_enabled(xe));
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CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
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if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
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return -ETIMEDOUT;
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if (xe->info.platform == XE_PVC) {
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xe_guc_rc_disable(guc);
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return 0;
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}
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if (xe->info.skip_guc_pc) {
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xe_gt_idle_enable_c6(gt);
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return 0;
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}
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return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
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}
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